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bh=tqjFs/IyP2PWeKlRmbAAWPZkIsNKkvhn10LBbn1RWTU=; b=GFYlkLtBUG+G9nLgkwz6eL7aoFEq9bwW/Eg1h/WvwIYZ9LVvbeHyaHRBLe385PaWd3s8h5 UETY1QeZcjfoijCgm1DDKE2p2dFQClNkVyRAe7ofxOwWpmIoB1Y/SP5XklpP7KQsj0fTTU gUTyHV4zR8cPJm+zwhRuxuHCWP6430R3QBFkM7zQVXsexur57Mf+lPX8Q9bUuPdLB+FPin iw4IscQJ0+fIwa8x9vHS+79DPs3ya2WRoJ7FBffSU+U5uAtIle7bDpD87Cd+c1qBWSf8zD agAHGAs6+aJ11TmN61BBMWAn2CanGdaZAd4xBZGzFMLSmeCDbH+wzuV126URRQ== Message-ID: <893f8b18-265e-4351-8d91-bd81f04c6eed@bootlin.com> Date: Mon, 13 Oct 2025 13:59:28 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 03/15] arm64: dts: allwinner: h616: add NAND controller To: =?UTF-8?Q?Jernej_=C5=A0krabec?= , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland Cc: Wentao Liang , =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= , Maxime Ripard , Thomas Petazzoni , linux-mtd@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org References: <20251010084042.341224-1-richard.genoud@bootlin.com> <20251010084042.341224-4-richard.genoud@bootlin.com> <4682810.LvFx2qVVIh@jernej-laptop> From: Richard GENOUD Content-Language: en-US, fr Organization: Bootlin In-Reply-To: <4682810.LvFx2qVVIh@jernej-laptop> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251013_045943_770964_23A93458 X-CRM114-Status: GOOD ( 16.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Le 11/10/2025 à 12:33, Jernej Škrabec a écrit : > Dne petek, 10. oktober 2025 ob 10:40:30 Srednjeevropski poletni čas je Richard Genoud napisal(a): >> The H616 has a NAND controller quite similar to the A10/A23 ones, but >> with some register differences, more clocks (for ECC and MBUS), more ECC >> strengths, so this requires a new compatible string. >> >> This patch adds the NAND controller node and pins in the device tree. >> >> Signed-off-by: Richard Genoud >> --- >> .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 50 +++++++++++++++++++ >> 1 file changed, 50 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi >> index ceedae9e399b..60626eba7f7c 100644 >> --- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi >> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi >> @@ -278,6 +278,37 @@ ir_rx_pin: ir-rx-pin { >> function = "ir_rx"; >> }; >> >> + nand_pins: nand-pins { >> + pins = "PC0", "PC1", "PC2", "PC5", "PC8", "PC9", >> + "PC10", "PC11", "PC12", "PC13", "PC14", >> + "PC15", "PC16"; >> + function = "nand0"; >> + }; >> + >> + nand_cs0_pin: nand-cs0-pin { >> + pins = "PC4"; >> + function = "nand0"; >> + bias-pull-up; >> + }; >> + >> + nand_cs1_pin: nand-cs1-pin { >> + pins = "PC3"; >> + function = "nand0"; >> + bias-pull-up; >> + }; >> + >> + nand_rb0_pin: nand-rb0-pin { >> + pins = "PC6"; >> + function = "nand0"; >> + bias-pull-up; >> + }; >> + >> + nand_rb1_pin: nand-rb1-pin { >> + pins = "PC7"; >> + function = "nand0"; >> + bias-pull-up; >> + }; >> + >> mmc0_pins: mmc0-pins { >> pins = "PF0", "PF1", "PF2", "PF3", >> "PF4", "PF5"; >> @@ -440,6 +471,25 @@ mmc2: mmc@4022000 { >> #size-cells = <0>; >> }; >> >> + nfc: nand-controller@4011000 { > > Nodes are sorted by memory address. So this one should be moved before > mmc2 and possibly others. Indeed. I'll fix that. > >> + compatible = "allwinner,sun50i-h616-nand-controller"; >> + reg = <0x04011000 0x1000>; >> + interrupts = ; >> + clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND0>, >> + <&ccu CLK_NAND1>, <&ccu CLK_MBUS_NAND>; >> + clock-names = "ahb", "mod", "ecc", "mbus"; >> + resets = <&ccu RST_BUS_NAND>; >> + reset-names = "ahb"; >> + dmas = <&dma 10>; >> + dma-names = "rxtx"; >> + pinctrl-names = "default"; >> + pinctrl-0 = <&nand_pins>, <&nand_cs0_pin>, >> + <&nand_cs1_pin>, <&nand_rb0_pin>, >> + <&nand_rb1_pin>; > > Are you sure that each nand device will use exactly this pin configuration? > IIUC, not all chips will have two CS and two RB pins. If so, pinctrl nodes > should be moved to device DT and pins subnodes should be marked with > /omit-if-no-ref/. You're right, all pins may not be used. Thanks! > > Best regards, > Jernej > >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + >> uart0: serial@5000000 { >> compatible = "snps,dw-apb-uart"; >> reg = <0x05000000 0x400>; >> -- Richard Genoud, Bootlin Embedded Linux and Kernel engineering https://bootlin.com