From: heiko@sntech.de (Heiko Stübner)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] clk: rockchip: fix clock select order for usbphy480m_src
Date: Sun, 16 Nov 2014 00:41:27 +0100 [thread overview]
Message-ID: <8965478.SpyRElfG0W@diego> (raw)
In-Reply-To: <1415866309-3277-1-git-send-email-kever.yang@rock-chips.com>
Am Donnerstag, 13. November 2014, 16:11:49 schrieb Kever Yang:
> According to rk3288 trm, the mux selector locate at bit[12:11]
> of CRU_CLKSEL13_CON shows:
> 2'b00: select HOST0 USB pll clock (clk_otgphy1)
> 2'b01: select HOST1 USB pll clock (clk_otgphy2)
> 2'b10: select OTG USB pll clock (clk_otgphy0)
>
> The clock map is in Fig. 3-4 CRU Clock Architecture Diagram 3
> - clk_otgphy0 -> USB PHY OTG
> - clk_otgphy1 -> USB PHY host0
> - clk_otgphy2 -> USB PHY host1
>
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
applied this to my clk branch for 3.19
Heiko
prev parent reply other threads:[~2014-11-15 23:41 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-13 8:11 [PATCH] clk: rockchip: fix clock select order for usbphy480m_src Kever Yang
2014-11-15 23:41 ` Heiko Stübner [this message]
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