From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04A66C433E1 for ; Thu, 27 Aug 2020 10:56:09 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C0F7422CB1 for ; Thu, 27 Aug 2020 10:56:08 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="vFIjVd8N" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C0F7422CB1 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=3QvKRHdYX+PfGSUlchyuu6XMiryVb5CK8ytQ46zaZnM=; b=vFIjVd8Ne2AU1o4LuF+uB8bSl 0EcKAoBSq/2IhsKksJCY20aeX88P3gmQ82FcmUt72O/peJq0v90EyY18hhAgT9/U/s2QCkgvg+DVm v2mSvKazlWDGUPcNErxNsY6KK7sadmpWZ/wfDUkVXlmTfxEVWJYitPiedizslEnWjDq7qoHnFCZCr JD91gvHFaInf6sy0u8BGwmzqhEvKm0eLfIjhDzdWH6jPh+HcA5eepn/T/q2+IvWO9ZPT0J4ELDKIc yeJxoa+/qUqH+ZCcziF2zkiI5tzj5qK6zj1PpApo2136p5870qlA1La5p5G26U3KvUYTeOZe7YcQX iN2FU5eZg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kBFYJ-000287-87; Thu, 27 Aug 2020 10:54:43 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kBFYG-00027O-Mz for linux-arm-kernel@lists.infradead.org; Thu, 27 Aug 2020 10:54:41 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6114C31B; Thu, 27 Aug 2020 03:54:39 -0700 (PDT) Received: from [192.168.1.190] (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 220DF3F68F; Thu, 27 Aug 2020 03:54:36 -0700 (PDT) Subject: Re: [PATCH 24/35] arm64: mte: Switch GCR_EL1 in kernel entry and exit To: Catalin Marinas , Andrey Konovalov References: <20200827103819.GE29264@gaia> From: Vincenzo Frascino Message-ID: <8affcfbe-b8b4-0914-1651-368f669ddf85@arm.com> Date: Thu, 27 Aug 2020 11:56:49 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200827103819.GE29264@gaia> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200827_065440_872610_BFE7D9D0 X-CRM114-Status: GOOD ( 25.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, Marco Elver , Elena Petrova , Kevin Brodsky , Will Deacon , Branislav Rankov , kasan-dev@googlegroups.com, linux-kernel@vger.kernel.org, linux-mm@kvack.org, Alexander Potapenko , Dmitry Vyukov , Andrey Ryabinin , Andrew Morton , Evgenii Stepanov Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 8/27/20 11:38 AM, Catalin Marinas wrote: > On Fri, Aug 14, 2020 at 07:27:06PM +0200, Andrey Konovalov wrote: >> diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S >> index cde127508e38..a17fefb0571b 100644 >> --- a/arch/arm64/kernel/entry.S >> +++ b/arch/arm64/kernel/entry.S >> @@ -172,6 +172,29 @@ alternative_else_nop_endif >> #endif >> .endm >> >> + /* Note: tmp should always be a callee-saved register */ > > Why callee-saved? Do you preserve it anywhere here? > Aargh, this is an old comment, I forgot to remove it after the last refactor. Thank you for pointing this out. >> + .macro mte_restore_gcr, el, tsk, tmp, tmp2 >> +#ifdef CONFIG_ARM64_MTE >> +alternative_if_not ARM64_MTE >> + b 1f >> +alternative_else_nop_endif >> + .if \el == 0 >> + ldr \tmp, [\tsk, #THREAD_GCR_EL1_USER] >> + .else >> + ldr_l \tmp, gcr_kernel_excl >> + .endif >> + /* >> + * Calculate and set the exclude mask preserving >> + * the RRND (bit[16]) setting. >> + */ >> + mrs_s \tmp2, SYS_GCR_EL1 >> + bfi \tmp2, \tmp, #0, #16 >> + msr_s SYS_GCR_EL1, \tmp2 >> + isb >> +1: >> +#endif >> + .endm >> + >> .macro kernel_entry, el, regsize = 64 >> .if \regsize == 32 >> mov w0, w0 // zero upper 32 bits of x0 >> @@ -209,6 +232,8 @@ alternative_else_nop_endif >> >> ptrauth_keys_install_kernel tsk, x20, x22, x23 >> >> + mte_restore_gcr 1, tsk, x22, x23 >> + >> scs_load tsk, x20 >> .else >> add x21, sp, #S_FRAME_SIZE >> @@ -386,6 +411,8 @@ alternative_else_nop_endif >> /* No kernel C function calls after this as user keys are set. */ >> ptrauth_keys_install_user tsk, x0, x1, x2 >> >> + mte_restore_gcr 0, tsk, x0, x1 >> + >> apply_ssbd 0, x0, x1 >> .endif >> >> @@ -957,6 +984,7 @@ SYM_FUNC_START(cpu_switch_to) >> mov sp, x9 >> msr sp_el0, x1 >> ptrauth_keys_install_kernel x1, x8, x9, x10 >> + mte_restore_gcr 1, x1, x8, x9 >> scs_save x0, x8 >> scs_load x1, x8 >> ret > > Since we set GCR_EL1 on exception entry and return, why is this needed? > We don't have a per-kernel thread GCR_EL1, it's global to all threads, > so I think cpu_switch_to() should not be touched. > I agree, we can remove it. We only require the kernel entry and the kernel exit ones. >> diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c >> index 7717ea9bc2a7..cfac7d02f032 100644 >> --- a/arch/arm64/kernel/mte.c >> +++ b/arch/arm64/kernel/mte.c >> @@ -18,10 +18,14 @@ >> >> #include >> #include >> +#include >> +#include >> #include >> #include >> #include >> >> +u64 gcr_kernel_excl __read_mostly; > > Could we make this __ro_after_init? > Yes, it makes sense, it should be updated only once through mte_init_tags(). Something to consider though here is that this might not be the right approach if in future we want to add stack tagging. In such a case we need to know the kernel exclude mask before any C code is executed. Initializing the mask via mte_init_tags() it is too late. I was thinking to add a compilation define instead of having gcr_kernel_excl in place. This might not work if the kernel excl mask is meant to change during the execution. Thoughts? >> + >> static void mte_sync_page_tags(struct page *page, pte_t *ptep, bool check_swap) >> { >> pte_t old_pte = READ_ONCE(*ptep); >> @@ -115,6 +119,13 @@ void * __must_check mte_set_mem_tag_range(void *addr, size_t size, u8 tag) >> return ptr; >> } >> >> +void mte_init_tags(u64 max_tag) >> +{ >> + u64 incl = ((1ULL << ((max_tag & MTE_TAG_MAX) + 1)) - 1); > > I'd rather use GENMASK here, it is more readable. > Agree, we can change it. -- Regards, Vincenzo _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel