Re: Question: SMMUv3 PMU event aliasing

[John Garry <john.garry@huawei.com>]

On 08/11/2021 12:19, Leo Yan wrote:
> Hi John,
> 
> [ + mailing list ]

Hi Leo,

> 
> I'd like to confirm the latest upstream status for SMMUv3 PMU event
> aliasing.
> 
> I see the patch set v6 of "perf pmu-events: Support event aliasing for
> system PMUs" [1] has been landed on the mainline kernel, and as an
> example, imx8mm DDR PMU has been supported as system PMU [2].
> 
> On the other hand, I can see patch set 5 contains the SMMUv3 PMU event
> aliasing with patch "perf vendor events arm64: Add Architected events
> smmuv3-pmcg.json" [3], but this patch was left out in patch set 6 and
> it's never landed on the mainline kernel.
> 
> Could you share current status (or plan) for upstreaming SMMUv3 PMU
> event alias?  Or if there have any block issue to prevent merging the
> changes in the mainline kernel?

This feature should be supported in the SMMUv3 PMU kernel driver and 
perf tool.

However it relies on the SMMU PMU identifier sysfs file to work. This 
relies on SMMU_PMCG_IIDR being set, which is introduced latest spec, 
which not much HW will support yet - see commit 2c255223362e. In theory 
we don't need that for the fixed, non-IMPDEF events, but I did not 
complicate perf tool with that mixed support.

That's the reason for which I paused smmuv3-pmcg.json upstream in [3]. I 
will revive that for new gen HW when concrete IMPDEF events known and 
shared.

Thanks,
John

> 
> Thanks for your help!
> 
> Leo
> 
> [1] https://lore.kernel.org/lkml/1607080216-36968-1-git-send-email-john.garry@huawei.com/
> [2] pmu-events/arch/arm64/freescale/imx8mm/sys/ddrc.json
> [3] https://lore.kernel.org/lkml/1604666153-4187-6-git-send-email-john.garry@huawei.com/
> .
> 


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