[PATCH 5/7] arm64: dts: ti: k3-j721s2-main: switch to 64-bit address space for PCIe1

Siddharth Vadapalli
2025-04-17T12:30:33Z

The PCIe1 instance of PCIe in J721S2 SoC supports:
1. 128 MB address region in the 32-bit address space
2. 4 GB address region in the 64-bit address space

The default configuration is that of a 128 MB address region in the
32-bit address space. While this might be sufficient for most use-cases,
it is insufficient for supporting use-cases which require larger address
spaces. Therefore, switch to using the 64-bit address space with a 4 GB
address region.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 92bf48fdbeba..da2fe83ddcf7 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -1394,7 +1394,7 @@ pcie1_rc: pcie@2910000 {
reg = <0x00 0x02910000 0x00 0x1000>,
<0x00 0x02917000 0x00 0x400>,
<0x00 0x0d800000 0x00 0x800000>,
- <0x00 0x18000000 0x00 0x1000>;
+ <0x41 0x00000000 0x00 0x1000>;
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
@@ -1412,8 +1412,9 @@ pcie1_rc: pcie@2910000 {
device-id = <0xb013>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
dma-coherent;
- ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
- <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
+ ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
+ <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */
+ <0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
--
2.34.1