Re: [PATCH 2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for PCIe1

Siddharth Vadapalli
2025-04-20T03:06:08Z

On Sat, Apr 19, 2025 at 11:35:50PM +0530, Kumar, Udit wrote:

Hello Udit,

>
> On 4/17/2025 5:34 PM, Siddharth Vadapalli wrote:
> > The PCIe0 instance of PCIe in J7200 SoC supports:
> > 1. 128 MB address region in the 32-bit address space
> > 2. 4 GB address region in the 64-bit address space
> >
> > The default configuration is that of a 128 MB address region in the
> > 32-bit address space. While this might be sufficient for most use-cases,
> > it is insufficient for supporting use-cases which require larger address
> > spaces. Therefore, switch to using the 64-bit address space with a 4 GB
> > address region.
> >
> > Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> > ---
> > arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 7 ++++---
> > 1 file changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> > index 5ab510a0605f..e898dffdebbe 100644
> > --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> > @@ -759,7 +759,7 @@ pcie1_rc: pcie@2910000 {
> > reg = <0x00 0x02910000 0x00 0x1000>,
> > <0x00 0x02917000 0x00 0x400>,
> > <0x00 0x0d800000 0x00 0x00800000>,
> > - <0x00 0x18000000 0x00 0x00001000>;
> > + <0x41 0x00000000 0x00 0x00001000>;
> > reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
> > interrupt-names = "link_state";
> > interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
> > @@ -778,8 +778,9 @@ pcie1_rc: pcie@2910000 {
> > device-id = <0xb00f>;
> > msi-map = <0x0 &gic_its 0x0 0x10000>;
> > dma-coherent;
> > - ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
> > - <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
> > + ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
> > + <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0x08000000>, /* 32-bit Non-Prefetchable MEM (128 MB) */
> > + <0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>; /* 64-bit Prefetchable MEM (4 GB - (129 MB + 4 KB)) */
>
> Sorry for novice question,
>
> with this change,  How do you see  old EP working which supports 32 bit
> addressing,
>
> or some translation is possible ?
>
> 0x43000000 0x41 0x08101000 0x41 0x08101000 0x00 0xf7eff000>
>
> to
>
> 0x63000000 0x00 0x08101000 0x41 0x08101000 0x00 0xf7eff000>

I didn't understand the question completely, but I shall try to explain
the changes being made which might possibly answer your question.

The ranges property for PCIe is different from the one for other
peripherals and is defined as described at:
https://elinux.org/Device_Tree_Usage#PCI_Address_Translation

With this patch series, the PCIe downstream devices - Switches, Endpoints -
will be assigned IO/Mem regions within the 64-bit CPU address space.

IO and 32-bit Non-Prefetchable MEM regions have the same PCIe Bus
Addresses as before which fall in the 32-bit PCIe Bus Address space.
It is only the newly added 64-bit Prefetchable MEM region that falls in
the 64-bit PCIe Bus Address space.

Please let me know if you require further clarification.

Regards,
Siddharth.