From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 00272C27C65 for ; Tue, 11 Jun 2024 16:14:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To: Subject:MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=xpaiwHWUg8gclRTfmWjxuwcVdDiblOMuTtWrJaUx/Hs=; b=y3q5QvtJ8ngiPf ITaZxkn61eUn+MWV72Or1hFG6vzj14ImedXsfGqCcVNs7Qng9riXGzjBpDZ5h5nxvoHnfDkNnePer 9H9yNwCIOyVgleNMehg1aVyqe+fjLaNkumdNMpjpefstt7GAR06XliUeQmoPvXLphY6vs8fidR3hA 7hiHIXMBRjenMOB5eWXlIfUKBb6eOLyeJrM1Ds4FYzHtzHrUpZhQjXU+WtTFn5vWHIdvS3xE/k9jB 6LO/EdfCb8h/BuWvT52A9ooxwkXRIkQurfhPSc8f0EX/af4V+7NDN/Ui7vdirH0p3Hcnpi7JnX2Ox Kleci9NwjWoFDj6aTdig==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sH48J-00000009Sv1-49SW; Tue, 11 Jun 2024 16:14:03 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sH48G-00000009SuH-3tDl for linux-arm-kernel@lists.infradead.org; Tue, 11 Jun 2024 16:14:02 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D7FD11595; Tue, 11 Jun 2024 09:14:23 -0700 (PDT) Received: from [10.57.41.181] (unknown [10.57.41.181]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 823083F73B; Tue, 11 Jun 2024 09:13:55 -0700 (PDT) Message-ID: <8c55de88-96ad-45a7-9be5-4f33f4266af2@arm.com> Date: Tue, 11 Jun 2024 17:13:49 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] perf: arm_pmuv3: Avoid assigning fixed cycle counter with threshold To: "Rob Herring (Arm)" , Will Deacon , Mark Rutland Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20240611155012.2286044-1-robh@kernel.org> Content-Language: en-US From: James Clark In-Reply-To: <20240611155012.2286044-1-robh@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240611_091401_053268_2631555A X-CRM114-Status: GOOD ( 20.43 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 11/06/2024 16:50, Rob Herring (Arm) wrote: > If the user has requested a counting threshold for the CPU cycles event, > then the fixed cycle counter can't be assigned as it lacks threshold > support. Currently, the thresholds will work or not randomly depending > on which counter the event is assigned. > > While using thresholds for CPU cycles doesn't make much sense, it can be > useful for testing purposes. > > Fixes: 816c26754447 ("arm64: perf: Add support for event counting threshold") > Signed-off-by: Rob Herring (Arm) > --- > drivers/perf/arm_pmuv3.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c > index 23fa6c5da82c..2612be29ee23 100644 > --- a/drivers/perf/arm_pmuv3.c > +++ b/drivers/perf/arm_pmuv3.c > @@ -939,9 +939,10 @@ static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc, > struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); > struct hw_perf_event *hwc = &event->hw; > unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT; > + bool has_threshold = !!(hwc->config_base & ARMV8_PMU_EVTYPE_TH); I was going to say doesn't it need to be (ARMV8_PMU_EVTYPE_TH | ARMV8_PMU_EVTYPE_TC) for it to give the same results as the hardware. But then I saw we only enable it if TH != 0, even if TC is set. And now I'm wondering if I inadvertently disabled a useful combination of options. The Arm ARM says it's only completely disabled when both TC and TH are 0. > > /* Always prefer to place a cycle counter into the cycle counter. */ > - if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) { > + if ((evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) && !has_threshold) { > if (!test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask)) > return ARMV8_IDX_CYCLE_COUNTER; > else if (armv8pmu_event_is_64bit(event) && _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel