From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C66CC52D7B for ; Tue, 13 Aug 2024 05:20:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=dCG9AaR1YwF6syqtcdaypvYNoSMCuxUcwyYT7v1PGHg=; b=rL47GlYJvc9aThvDfasB/sciWW CpiMavtythGW6EOfLVBFnhCgF5OAJ11zhKcTyGXeXEWRLP7hlw1vEl9y4Hdy6/2EkTnsvd7d9DAPE S28w1tOXfvgpitUuglU0A9ynD18m/bQmK3HBghZKa9YzvyvecfwrnKBpbVUXq6v6W5+eXCJA/On+5 9DXFUWDWnUq++2XDlTcHvbuzuvD/TDi2dJ0LuIPA6d0XH1pN3d2cCmk/JdJxkLF/8KPrHjmlWe9N3 9P7NPQd217uqwQFoWOy3oZW7gYQe9Nv1M0+flqbWFRcVdwWS8tH8VgO2mIZNowemBlsiacJJ6JvX1 0i410LRA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sdjxb-00000002R9m-2eQ5; Tue, 13 Aug 2024 05:20:43 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sdjwz-00000002R7U-1AJu for linux-arm-kernel@lists.infradead.org; Tue, 13 Aug 2024 05:20:06 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BB919FEC; Mon, 12 Aug 2024 22:20:29 -0700 (PDT) Received: from [10.163.57.59] (unknown [10.163.57.59]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EE02C3F40C; Mon, 12 Aug 2024 22:20:02 -0700 (PDT) Message-ID: <8cc5014a-ecac-4783-9b91-437c056afac8@arm.com> Date: Tue, 13 Aug 2024 10:50:00 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [boot-wrapper] aarch64: Enable access into FEAT_FGT2 registers from EL2 and below To: linux-arm-kernel@lists.infradead.org Cc: mark.rutland@arm.com References: <20240730054643.157295-1-anshuman.khandual@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: <20240730054643.157295-1-anshuman.khandual@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240812_222005_413277_68CA4A65 X-CRM114-Status: GOOD ( 15.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 7/30/24 11:16, Anshuman Khandual wrote: > FEAT_FGT2 adds system registers HDFGRTR2_EL2, HDFGWTR2_EL2, HFGITR2_EL2, > HFGRTR2_EL2 and HFGWTR2_EL2. But access into these system registers from > EL2 and below exception levels, will trap into EL3 unless SCR_EL3.FGTEN2 > is set. > > Enable access to FEAT_FGT2 registers when they are implemented. Given that > these new FEAT_FGT2 trap registers have fields that reset to UNKNOWN values > when resets are taken to EL3, this initialises all registers as cleared. > > Signed-off-by: Anshuman Khandual > --- > This picks up from an earlier discussion regarding [PATCH 2/2]. > > https://lore.kernel.org/all/20240404073726.947215-1-anshuman.khandual@arm.com/ > > arch/aarch64/include/asm/cpu.h | 7 +++++++ > arch/aarch64/init.c | 9 +++++++++ > 2 files changed, 16 insertions(+) > > diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h > index a5744e1..878d03d 100644 > --- a/arch/aarch64/include/asm/cpu.h > +++ b/arch/aarch64/include/asm/cpu.h > @@ -23,6 +23,12 @@ > #define SCTLR2_EL1 s3_0_c1_c0_3 > #define SCTLR2_EL2 s3_4_c1_c0_3 > > +#define HDFGRTR2_EL2 s3_4_c3_c1_0 > +#define HDFGWTR2_EL2 s3_4_c3_c1_1 > +#define HFGRTR2_EL2 s3_4_c3_c1_2 > +#define HFGWTR2_EL2 s3_4_c3_c1_3 > +#define HFGITR2_EL2 s3_4_c3_c1_7 > + > /* > * RES1 bit definitions definitions as of ARM DDI 0487G.b > * > @@ -63,6 +69,7 @@ > #define SCR_EL3_SCTLR2En BIT(44) > #define SCR_EL3_PIEN BIT(45) > #define SCR_EL3_D128En BIT(47) > +#define SCR_EL3_FGTEN2 BIT(59) > > #define HCR_EL2_RES1 BIT(1) > > diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c > index c9fc7f1..b4d64a0 100644 > --- a/arch/aarch64/init.c > +++ b/arch/aarch64/init.c > @@ -68,6 +68,15 @@ void cpu_init_el3(void) > if (mrs_field(ID_AA64MMFR0_EL1, FGT)) > scr |= SCR_EL3_FGTEN; > > + if (mrs_field(ID_AA64MMFR0_EL1, FGT) >= 2) { > + scr |= SCR_EL3_FGTEN2; > + msr(HDFGRTR2_EL2, 0); > + msr(HDFGWTR2_EL2, 0); > + msr(HFGITR2_EL2, 0); > + msr(HFGRTR2_EL2, 0); > + msr(HFGWTR2_EL2, 0); > + } > + > if (mrs_field(ID_AA64MMFR0_EL1, ECV) >= 2) > scr |= SCR_EL3_ECVEN; > Hello Mark, Does this patch look okay ? Clearing all FEAT_FGT2 based trap registers ensures that all individual feature registers access will trap into EL2 given that they are all of inverse polarity. Also unlike FEAT_FGT their corresponding features are currently unused in the kernel. Please do let me know if anything needs to be changed here. Thank you. - Anshuman