From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3913FCD1283 for ; Mon, 1 Apr 2024 05:31:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Content-ID:In-Reply-To: References:Message-ID:Date:Subject:CC:To:From:Reply-To:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=47YlhbODDvaVQkQ1lHFpxgrt7qsSjwHRocq/6kH2SAY=; b=pTEl/l2wsmE+nZ dqS6eYv4cf96PP8JzzRK6R+tdf/kfRKIm0NCX06DHN80cwsbpIc4veTMwKbZvcFWfavNNVwrtKkvD JGGPEpRenslzlh0JErR0yoLbejRp95HbhdtU+0Cb8XpF/Y/UvfjW4Q6UEnNlTl81a6K/EaQv5wYZi jF6vXpwAldo42KUJm1bXkjcgtPKs0jKm0nnI9lXL0uSEjC1GlrdQ7yyWVirCc6GWTsvL57I9LWYqG WwpImrkh5hLhoQgCoMtBzyiQVT+BPAGYnu2QJWP1H9MdE9K7SaTIdeg3K5HLqP00yw1W1Ge59BucE xe0nKG5HQIHrJysSx4PQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrAGh-00000006xgL-0VeA; Mon, 01 Apr 2024 05:31:39 +0000 Received: from mailgw01.mediatek.com ([216.200.240.184]) by bombadil.infradead.org with esmtps (Exim 4.97.1 #2 (Red Hat Linux)) id 1rrAGe-00000006xfJ-06yr; Mon, 01 Apr 2024 05:31:37 +0000 X-UUID: 1829ae32efe911eeac1957ae9f99f617-20240331 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=MIME-Version:Content-Transfer-Encoding:Content-ID:Content-Type:In-Reply-To:References:Message-ID:Date:Subject:CC:To:From; bh=5T7SBoFIaUnGz49jTEt6E+UfPRm0nKf9A5mLlUhyTqE=; b=skIP5IGdJqFo8z9EISnj0qHx2lMQJueJ0L+h18IaRWnMVnHpWELRgY357ecM/vbb7rEd+EdVd8WIBEEhXkmlvKKmQ/f3xsFZZ5W7wthNwuVPl4y+eOpE058hN0bAc/CrRvmZU4IDGiT/Zd+hAV45x/ah+g+QVTLdYm5q0HsAC8A=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.37,REQID:b7876603-36c5-4de2-8371-d90a2ac34ebd,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:6f543d0,CLOUDID:d5918e00-c26b-4159-a099-3b9d0558e447,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES :1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 1829ae32efe911eeac1957ae9f99f617-20240331 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (musrelay.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1697814971; Sun, 31 Mar 2024 22:31:30 -0700 Received: from mtkmbs10n1.mediatek.inc (172.21.101.34) by MTKMBS14N2.mediatek.inc (172.21.101.76) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 1 Apr 2024 13:31:27 +0800 Received: from APC01-PSA-obe.outbound.protection.outlook.com (172.21.101.237) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 1 Apr 2024 13:31:27 +0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=IfoP1eAO0DxNsLGicheZCHQb5vZJoHex/MWSl2Z4IwMQJX3S3cC4/AM5koIZSs5c6C+JIsxsEowRtrIhxWoU/Z5+37yv+yOYjgucfEF3yUb0Myhb3dMwYf9XJzMShPdlvwu0E1CdcVLczlpjxwitGpAnUtGd94E6qoEDSkGyXxeJW13TOpVvbEaPzRSuJAICyR+wuU7dwryd5ZItX2UxJL2AUG08yQ5a0TqMBUy4+ey5F9aEP5UbIMhSh5oQXXASPUiFTA9x5Dd2/ofkEFwfRmDU0YrIKRxU3Lh6aDkG5lAUtAkMI3xaHVWhAFeSpFsEbheYId4hcb0eosdLHms8RA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=5T7SBoFIaUnGz49jTEt6E+UfPRm0nKf9A5mLlUhyTqE=; b=PDNeQeLgPeWXdgJJSSBmKzTwWBcGb/j8IHB2kVA1pTPl8enHUT6v+wImtuIWMBjdry6vcWY8RsOOr1NnRNnQ+OoB4Htp1vO8MQ9sDqREydW6mHA8Ah6+CkW15IAF69tTDfMsvf4pkv/V/ZGqArwtFyBYvm8pURW+LpcE0RPpNt7cgE0xGvL4KUMKXj+x6xfbhTmxyqWPIq5H1uz0cWnR+HXBP6PQlGAnT/Zr1/q+gMOgYcNGeVrdQtnQ7e0fDYRDpQWii4ghLy8dn/ua64ZiIPWhBH90F9ohPT2cY2msuKEw0imosmZxfF6PDVU27RW/Ea4NCGRjJCadhLdgVUk4fg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=mediatek.com; dmarc=pass action=none header.from=mediatek.com; dkim=pass header.d=mediatek.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mediateko365.onmicrosoft.com; s=selector2-mediateko365-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=5T7SBoFIaUnGz49jTEt6E+UfPRm0nKf9A5mLlUhyTqE=; b=uKNjYUhGfsWpgJZosGI9BGoqNML96x2ncTdLBULETOcu/g+HcwopMbg/3RzsFRQhhdPHoZGMt2a1VNCmcDnEQVU4j1TT+HHCC//6ySAYAtQ/D5IAzrEQO6M//jhP53s1akwbdRYqCmf7J6IP7j9Kd4op+TLDp7uFi0scnOlvHhA= Received: from TYZPR03MB6624.apcprd03.prod.outlook.com (2603:1096:400:1f4::13) by SEYPR03MB6674.apcprd03.prod.outlook.com (2603:1096:101:6b::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7409.45; Mon, 1 Apr 2024 05:31:22 +0000 Received: from TYZPR03MB6624.apcprd03.prod.outlook.com ([fe80::f3b6:91a7:e0fb:cb27]) by TYZPR03MB6624.apcprd03.prod.outlook.com ([fe80::f3b6:91a7:e0fb:cb27%7]) with mapi id 15.20.7409.042; Mon, 1 Apr 2024 05:31:21 +0000 From: =?utf-8?B?Q0sgSHUgKOiDoeS/iuWFiSk=?= To: =?utf-8?B?U2hhd24gU3VuZyAo5a6L5a2d6KyZKQ==?= , "chunkuang.hu@kernel.org" , "angelogioacchino.delregno@collabora.com" CC: "linux-mediatek@lists.infradead.org" , "linux-kernel@vger.kernel.org" , =?utf-8?B?QmliYnkgSHNpZWggKOisnea/n+mBoCk=?= , "jason-ch.chen@mediatek.corp-partner.google.com" , =?utf-8?B?TmFuY3kgTGluICjmnpfmrKPonqIp?= , "daniel@ffwll.ch" , "p.zabel@pengutronix.de" , "dri-devel@lists.freedesktop.org" , "airlied@gmail.com" , "sean@poorly.run" , "matthias.bgg@gmail.com" , "fshao@chromium.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v6 12/14] drm/mediatek: Support CRC in display driver Thread-Topic: [PATCH v6 12/14] drm/mediatek: Support CRC in display driver Thread-Index: AQHafBnuyYE4/yZWBUuc+dcK3AS/vbFS83MA Date: Mon, 1 Apr 2024 05:31:21 +0000 Message-ID: <8dc7ca6547190c4ff8fccb50cda790884a03fc32.camel@mediatek.com> References: <20240322052829.9893-1-shawn.sung@mediatek.com> <20240322052829.9893-13-shawn.sung@mediatek.com> In-Reply-To: <20240322052829.9893-13-shawn.sung@mediatek.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: TYZPR03MB6624:EE_|SEYPR03MB6674:EE_ x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: juZiw+3jH4zQSMd3E0ruiE+SIDwdWc1a/X1E5l/9r1/3+H3n+gH8CQEuyrARhXzdnfx/hnN6QSvAsSc7Aup76qBGZkJCElQgGkwS0ylOph5PiKX6YpFbsGW9kyOrPpxxQAxhH3kpjGXSZRy1AQsSEID2an7vzQJ5dPlkPRbwWyjehPvsfvuyFKuYriGompXYBMuWJutNzBsAuz2E180lSlH2QIhpl2jNkWgY7SKPpUzbh0bu6JFtIDFv5k0CiTfF2JvmGghYU2nVXtM59EFo65FQv01HONQyzkXjCb12kYZzPocXpNdzwAW/LB0rRSvTTDyCzOPXCCmjqRZW6bnBvyR1/OpofF4+ujpYsT9WOglHj4f1rZS0vOnWYbKrihe1sVm368QQBXQV/AY+hTn578dzXrc+BDNXLCQb9P85ET51XQ4hZ4cVL9OprmWBlkDXOsHOUcIxnnk/nsWz3R8u68ioGe6Tk7vmyqy4hSFHmL8KjUIdLLuJk+oS9Lvozp2kD8ahJVEs423reYksqlrn6TN7oWJK34kdcW7I1UZmAZt26Z6rzZUcQIqHpyviFXcVDL2Bxlv5Ob9wWTsvh2We3wAZDFJn156Z7mrZ+rhfHaPqGOjM/fyWiMn0ufSs7/nMgKTZ2co5WtoWfWv+OVYGooWe5PJTFjU+7pLBIBgB9V8= x-forefront-antispam-report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:TYZPR03MB6624.apcprd03.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230031)(1800799015)(366007)(7416005)(376005);DIR:OUT;SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?utf-8?B?aGw5K3JaVHIyRWd2dzE3VWp5Qmx1a0kzNlR1a2lxRkNFNFcwQ3hZOFRONVda?= =?utf-8?B?eWh1WnBaVytjbUNIczZIQ0xVV25nUC9HOENYSUl0UlIwamtzY001RmZuMEJr?= =?utf-8?B?RGxDcHlkZlFXOVg0YW9CN3VweWwyRklGcU16ZzUzTlJhWGx4cnlFYVJscFVi?= =?utf-8?B?bHMyUU00WnFGbEdIdDVJem9lemJxK3RXcFhJYTY3R2RUaU1DUXBodFpsdWV5?= =?utf-8?B?YWpRTW9FMFMzaFZKQjJaeFhrK0RRL0NUSHpjS21MNzA1ZUI3ODhUZ1pwSDJ4?= =?utf-8?B?Z2Q4SmVMYjV4bGJST1lnbDhPejM0RC91WjkrbUMydzdLcmUxT2Q5Rk5HMnYv?= =?utf-8?B?eTB3ZXJ2Qm9zY2JPSklMMXF6eEg5aDJEcFJtbTFKcW5FMGFlcFZPelFiN1lL?= =?utf-8?B?a3NtV2lJUEg4RHlaYkdFTVk5bXRJazI5RStLOFZETXo1SHA4TTREWjdsSjVE?= =?utf-8?B?QnFBL0owakR4RUVkQ21nSDBXcTFrcmZ3R1FWSDNEM3NwTDJOaHprVHN4cDdN?= =?utf-8?B?YkJJY1pRSHlWZVRSZmMrOW5RV1NQUm9GTjZ3MEVrVUxaSnRwQTI5NjJ6cEQr?= =?utf-8?B?RFcyR1hzM3FjemxtWUplV1pYZVRnQ0RETDU1UHhNRjViNW1Ea29scHNuMW5C?= =?utf-8?B?ZUpDVkJYTk1zSDU3b2hrLzU4bnBMTUNoVTVKOTBoNGhDN0IyVU52RjlzblM1?= =?utf-8?B?VU14V2E2bEJMVElQMU1VZHh1QndwR0IvYUkySHFBQWRkQjk2Q00wUHd4NHlR?= =?utf-8?B?U0lnOTByb0NnNkcxZDFLK2k1U0VQa2JEM1dTSUkvRHM2dUpMdzNtZEJGUmg0?= =?utf-8?B?U2lXUFNRbGk2VVFPNTJsUnp3ZkpWMTNaTlQxTkw3VnlpVTc3RlY2VUpNV2FL?= =?utf-8?B?QWErMHZGcWxVUEVhTzY2TEw4cFNSOHFIZTBEakZLOHYxTE1xblJ4eEIvQXQv?= =?utf-8?B?MjRMT0N3bnU5QkRqalkva1JldUJnZkpieVVib0F2aXdVaW1rSk1mUUJRaE8z?= =?utf-8?B?RTVFQkhzSW9GZFh3aHFpOXpmZzNwTmMwWk9ibzVwUkhGNm5md0hMUUd5Vmth?= =?utf-8?B?TWRpTkM5YnVHekFpREEvRmkwTjNkRW04TW5oVFhmNzk3Z045RXhPQk92SW15?= =?utf-8?B?eEdvZ0N2eWo4SzdZdzdNOTRuU04rd0NydFpXckx2RldsdUlLMDFsZGZIU2pk?= =?utf-8?B?M1haT0tMQW5ob3h4OTZoSlRXR2R4cDNCSHJYRTVTVTM4dEE2NXVveVlkSHJh?= =?utf-8?B?RHQ0Z3FtdFMvU3VOeFZCZEE5SWRFbUZkSUhBZldOWjNldDJsd3o1bDZTYUx0?= =?utf-8?B?QWN1WTd0QzRjTEdUVXhvbjdzaFlvRE1xcDZBbUZYOW8yRmFOZUt1dU05MFFK?= =?utf-8?B?SysxeDl2UHVjOEQ3RGZyZlI4SHJ1SVhjSWpQMGdJUG5tSFZ4RVlhSkVhV1Bn?= =?utf-8?B?R3k0UUszcHdRZWIyeG9EeHJ2WXRRTzFUNGdSZUtXSEMvMWh0ZmNvOEJ2K3Y3?= =?utf-8?B?LzN5ZFBYa0Q2NHVGd1VUTkNLci9XbkhlUnNkZlR0Z01Mc1NsL1dHVFBZS0l5?= =?utf-8?B?V25WU2E3SnUyWHhmSFNGYTkwNm5Fd29RazNObnpFS0JyWk9Tb1VYT2RsTTdv?= =?utf-8?B?QXVOOSt5MFlBRmdyZUZIeWgwMjM2QmIzZ3ZEQ1VTdXF3NjdhWHRYcFlWdUlm?= =?utf-8?B?ZGxNbjhhODl5YjNRbmRKb2VJbUxhcFdLdEFQRWpNSTVsSE5ZMzVDM2xuUG5x?= =?utf-8?B?allWaDBraHZTUFZyNXNTVG9XMTZsYmIvM0lDZW91bmw5aFFlK3dwK0ZEN2gy?= =?utf-8?B?cis0MlQvTm81ajdoWm1TcHp5bndNOXk3M0ozbGFqTVg5TFFPWnlOY1FVRWdV?= =?utf-8?B?WThMTHRTamtFem56ZzlUVC9PMnFYclczajVRbXAwMnM3dVh1cFBMNkh6bUlI?= =?utf-8?B?OHRKSFUrUVc1bXdXL25OcGFWazFhU0Npc21jSGVlSForRjc2WTRtdTNKSHI4?= =?utf-8?B?VXZWMVZ6dXB2dEhWR2hWUGQrYWFyS1lNL0V1RDgydEo3LzVjM2kvMlBodVVV?= =?utf-8?B?WjFqbk52OTlLZWU0RHJEMU10b2VTNUFzdzZBQ2JZbE4wQlkxbi9obURtOTZJ?= =?utf-8?Q?xdol5jElBayZAWVzyyw/2QcQD?= Content-ID: <999DC7FB76A636499054D5047AEE80C7@apcprd03.prod.outlook.com> MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TYZPR03MB6624.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5e559d6a-3949-4fbe-1fa2-08dc520cf6a8 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Apr 2024 05:31:21.0706 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a7687ede-7a6b-4ef6-bace-642f677fbe31 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: kWmMGSWw5C3SjmcPfgiSQnCEi08/UN1QDzr8pycYaEQiJYXV4TokmS9UbHwEkUvdu5ohJZL87r+t63ztl+GQhA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEYPR03MB6674 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--17.185000-8.000000 X-TMASE-MatchedRID: z5DqD3Ob670OwH4pD14DsPHkpkyUphL9X4GSJGyYc35HZg0gWH5yUZ2i jX3Hwio1GQdEeHBaW03ijpjet3oGSB1lbFt9ZuyRW7gz/Gbgpl5t3qsaFY4DBAqiCYa6w8tvBsT xCacZZxVdMHCwJnaEwVPf24S03K9j8ZTibkDR5X2zI1v7J4hECgS7cfuuBhWpDZjzHLL3eRb4U6 vP1jLLb5SZZYdK0V3k8uL0miYDZXME7MuQrZP2o47Su3QulAZ5loU71ctjXZTUM0gUto0wuHWCd 6QvVzbeotXGpX88Erd9v84PYRXkEFfdwZmjAXfzGVyS87Wb4lyIrmqDVyayv26UuCiCh1o8Iw64 a0XgvUQRlDCAAgwkvBVo+7txs4NtP3l/3kVpN0V2aFFWhkT3QF67veYUroY0V9eB8vnmKe+VnOr Hx1EE6zkHYTmBMYNWYZKi2GGnn9+yRDt3x3st98OD5TU1KZy5u56wFPSkMVElP1vFxquW9kQy8b tyURq0JUfMPsUzHOKX9RBfHVAigYxYkErIAqjR58dk5sbwmyh+tO36GYDlsqvM+zzl/BST0gELN 9U+w7HDpuLJ3freRQgfAV4aPxAmtAOuXrON8jbuykw7cfAoIH0tCKdnhB58pTwPRvSoXL2y5/tF Zu9S3Ku6xVHLhqfxIAcCikR3vq/aWj2BY1CdyxLb9Bec6JeSaDVAF1LsOkbwZJd1ZvL3FFtSw2L 4HKaT X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--17.185000-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 738E89C7D68FA179CF8B08C4801CF09E26B03888228F1E80BD49BA331B8D03762000:8 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240331_223136_128357_1CCFAC99 X-CRM114-Status: GOOD ( 21.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, Shawn: On Fri, 2024-03-22 at 13:28 +0800, Shawn Sung wrote: > From: Hsiao Chien Sung > > Register CRC related function pointers to support > CRC retrieval. > > Signed-off-by: Hsiao Chien Sung > --- > drivers/gpu/drm/mediatek/mtk_crtc.c | 260 > ++++++++++++++++++++++++ > drivers/gpu/drm/mediatek/mtk_crtc.h | 38 ++++ > drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 3 + > 3 files changed, 301 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c > b/drivers/gpu/drm/mediatek/mtk_crtc.c > index d811e4e73a36c..6440c5fb336d7 100644 > --- a/drivers/gpu/drm/mediatek/mtk_crtc.c > +++ b/drivers/gpu/drm/mediatek/mtk_crtc.c > @@ -18,6 +18,7 @@ > #include > #include > #include > +#include > > #include "mtk_crtc.h" > #include "mtk_ddp_comp.h" > @@ -69,6 +70,9 @@ struct mtk_crtc { > /* lock for display hardware access */ > struct mutex hw_lock; > bool config_updating; > + > + struct mtk_ddp_comp *crc_provider; > + struct drm_vblank_work crc_work; > }; > > struct mtk_crtc_state { > @@ -703,6 +707,71 @@ static void mtk_crtc_update_output(struct > drm_crtc *crtc, > } > } > > +static void mtk_crtc_crc_work(struct kthread_work *base) > +{ > + struct drm_vblank_work *work = to_drm_vblank_work(base); > + struct mtk_crtc *mtk_crtc = > + container_of(work, typeof(*mtk_crtc), crc_work); > + > + if (mtk_crtc->base.crc.opened) { > + struct mtk_ddp_comp *comp = mtk_crtc->crc_provider; > + u64 vblank = drm_crtc_vblank_count(&mtk_crtc->base); > + > + comp->funcs->crc_read(comp->dev); > + > + /* could take more than 50ms to finish */ > + drm_crtc_add_crc_entry(&mtk_crtc->base, true, vblank, > + comp->funcs->crc_entry(comp- > >dev)); It seems that you could regenerate cmdq packet for crc here. So crtc atomic flush and crc could use the same mailbox channel. Regards, CK > + > + drm_vblank_work_schedule(&mtk_crtc->crc_work, vblank + > 1, true); > + } > +} > + > +static int mtk_crtc_set_crc_source(struct drm_crtc *crtc, const char > *src) > +{ > + struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc); > + > + if (!src) > + return -EINVAL; > + > + if (strcmp(src, "auto") != 0) { > + DRM_ERROR("%s(crtc-%d): unknown source '%s'\n", > + __func__, drm_crtc_index(crtc), src); > + return -EINVAL; > + } > + > + /* > + * skip the first crc because the first frame (vblank + 1) is > configured > + * by mtk_crtc_ddp_hw_init() when atomic enable > + */ > + drm_vblank_work_schedule(&mtk_crtc->crc_work, > + drm_crtc_vblank_count(crtc) + 2, > false); > + return 0; > +} > + > +static int mtk_crtc_verify_crc_source(struct drm_crtc *crtc, const > char *src, > + size_t *cnt) > +{ > + struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc); > + struct mtk_ddp_comp *comp = mtk_crtc->crc_provider; > + > + if (!comp) { > + DRM_ERROR("%s(crtc-%d): no crc provider\n", > + __func__, drm_crtc_index(crtc)); > + return -ENOENT; > + } > + > + if (src && strcmp(src, "auto") != 0) { > + DRM_ERROR("%s(crtc-%d): unknown source '%s'\n", > + __func__, drm_crtc_index(crtc), src); > + return -EINVAL; > + } > + > + *cnt = comp->funcs->crc_cnt(comp->dev); > + > + return 0; > +} > + > int mtk_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane > *plane, > struct mtk_plane_state *state) > { > @@ -751,6 +820,8 @@ static void mtk_crtc_atomic_enable(struct > drm_crtc *crtc, > > drm_crtc_vblank_on(crtc); > mtk_crtc->enabled = true; > + > + drm_vblank_work_init(&mtk_crtc->crc_work, crtc, > mtk_crtc_crc_work); > } > > static void mtk_crtc_atomic_disable(struct drm_crtc *crtc, > @@ -840,6 +911,8 @@ static const struct drm_crtc_funcs mtk_crtc_funcs > = { > .atomic_destroy_state = mtk_crtc_destroy_state, > .enable_vblank = mtk_crtc_enable_vblank, > .disable_vblank = mtk_crtc_disable_vblank, > + .set_crc_source = mtk_crtc_set_crc_source, > + .verify_crc_source = mtk_crtc_verify_crc_source, > }; > > static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = { > @@ -1033,6 +1106,11 @@ int mtk_crtc_create(struct drm_device > *drm_dev, const unsigned int *path, > > if (comp->funcs->ctm_set) > has_ctm = true; > + > + if (comp->funcs->crc_cnt && > + comp->funcs->crc_entry && > + comp->funcs->crc_read) > + mtk_crtc->crc_provider = comp; > } > > mtk_ddp_comp_register_vblank_cb(comp, mtk_crtc_ddp_irq, > @@ -1136,3 +1214,185 @@ int mtk_crtc_create(struct drm_device > *drm_dev, const unsigned int *path, > > return 0; > } > + > +void mtk_crtc_init_crc(struct mtk_crtc_crc *crc, const u32 > *crc_offset_table, > + size_t crc_count, u32 reset_offset, u32 > reset_mask) > +{ > + crc->ofs = crc_offset_table; > + crc->cnt = crc_count; > + crc->rst_ofs = reset_offset; > + crc->rst_msk = reset_mask; > + crc->va = kcalloc(crc->cnt, sizeof(*crc->va), GFP_KERNEL); > + if (!crc->va) { > + DRM_ERROR("failed to allocate memory for crc\n"); > + crc->cnt = 0; > + } > +} > + > +void mtk_crtc_read_crc(struct mtk_crtc_crc *crc, void __iomem *reg) > +{ > + if (!crc->cnt || !crc->ofs || !crc->va) > + return; > + > +#if IS_REACHABLE(CONFIG_MTK_CMDQ) > + /* sync to see the most up-to-date copy of the DMA buffer */ > + dma_sync_single_for_cpu(crc->cmdq_client.chan->mbox->dev, > + crc->pa, crc->cnt * sizeof(*crc->va), > + DMA_FROM_DEVICE); > +#endif > +} > + > +void mtk_crtc_destroy_crc(struct mtk_crtc_crc *crc) > +{ > + if (!crc->cnt) > + return; > + > +#if IS_REACHABLE(CONFIG_MTK_CMDQ) > + if (crc->pa) { > + dma_unmap_single(crc->cmdq_client.chan->mbox->dev, > + crc->pa, crc->cnt * sizeof(*crc->va), > + DMA_TO_DEVICE); > + crc->pa = 0; > + } > + if (crc->cmdq_client.chan) { > + mtk_drm_cmdq_pkt_destroy(&crc->cmdq_handle); > + mbox_free_channel(crc->cmdq_client.chan); > + crc->cmdq_client.chan = NULL; > + } > +#endif > + kfree(crc->va); > + crc->va = NULL; > + crc->cnt = 0; > +} > + > +#if IS_REACHABLE(CONFIG_MTK_CMDQ) > +/** > + * mtk_crtc_create_crc_cmdq - Create a CMDQ thread for syncing the > CRCs > + * @dev: Kernel device node of the CRC provider > + * @crc: Pointer of the CRC to init > + * > + * This function will create a looping thread on GCE (Global Command > Engine) to > + * keep the CRC up to date by monitoring the assigned event (usually > the frame > + * done event) of the CRC provider, and read the CRCs from the > registers to a > + * shared memory for the workqueue to read. To start/stop the > looping thread, > + * please call `mtk_crtc_start_crc_cmdq()` and > `mtk_crtc_stop_crc_cmdq()` > + * defined blow. > + * > + * The reason why we don't update the CRCs with CPU is that the > front porch of > + * 4K60 timing in CEA-861 is less than 60us, and register read/write > speed is > + * relatively unreliable comparing to GCE due to the bus design. > + * > + * We must create a new thread instead of using the original one for > plane > + * update is because: > + * 1. We cannot add another wait-for-event command at the end of > cmdq packet, or > + * the cmdq callback will delay for too long > + * 2. Will get the CRC of the previous frame if using the existed > wait-for-event > + * command which is at the beginning of the packet > + */ > +void mtk_crtc_create_crc_cmdq(struct device *dev, struct > mtk_crtc_crc *crc) > +{ > + int i; > + > + if (!crc->cnt) { > + dev_warn(dev, "%s: not support\n", __func__); > + goto cleanup; > + } > + > + if (!crc->ofs) { > + dev_warn(dev, "%s: not defined\n", __func__); > + goto cleanup; > + } > + > + crc->cmdq_client.client.dev = dev; > + crc->cmdq_client.client.tx_block = false; > + crc->cmdq_client.client.knows_txdone = true; > + crc->cmdq_client.client.rx_callback = NULL; > + crc->cmdq_client.chan = mbox_request_channel(&crc- > >cmdq_client.client, 0); > + if (IS_ERR(crc->cmdq_client.chan)) { > + dev_warn(dev, "%s: failed to create mailbox client\n", > __func__); > + crc->cmdq_client.chan = NULL; > + goto cleanup; > + } > + > + if (mtk_drm_cmdq_pkt_create(&crc->cmdq_client, &crc- > >cmdq_handle, PAGE_SIZE)) { > + dev_warn(dev, "%s: failed to create cmdq packet\n", > __func__); > + goto cleanup; > + } > + > + if (!crc->va) { > + dev_warn(dev, "%s: no memory\n", __func__); > + goto cleanup; > + } > + > + /* map the entry to get a dma address for cmdq to store the crc > */ > + crc->pa = dma_map_single(crc->cmdq_client.chan->mbox->dev, > + crc->va, crc->cnt * sizeof(*crc->va), > + DMA_FROM_DEVICE); > + > + if (dma_mapping_error(crc->cmdq_client.chan->mbox->dev, crc- > >pa)) { > + dev_err(dev, "%s: failed to map dma\n", __func__); > + goto cleanup; > + } > + > + if (crc->cmdq_event) > + cmdq_pkt_wfe(&crc->cmdq_handle, crc->cmdq_event, true); > + > + for (i = 0; i < crc->cnt; i++) { > + /* put crc to spr1 register */ > + cmdq_pkt_read_s(&crc->cmdq_handle, crc->cmdq_reg- > >subsys, > + crc->cmdq_reg->offset + crc->ofs[i], > + CMDQ_THR_SPR_IDX1); > + > + /* copy spr1 register to physical address of the crc */ > + cmdq_pkt_assign(&crc->cmdq_handle, CMDQ_THR_SPR_IDX0, > + CMDQ_ADDR_HIGH(crc->pa + i * > sizeof(*crc->va))); > + cmdq_pkt_write_s(&crc->cmdq_handle, CMDQ_THR_SPR_IDX0, > + CMDQ_ADDR_LOW(crc->pa + i * > sizeof(*crc->va)), > + CMDQ_THR_SPR_IDX1); > + } > + /* reset crc */ > + mtk_ddp_write_mask(&crc->cmdq_handle, ~0, crc->cmdq_reg, 0, > + crc->rst_ofs, crc->rst_msk); > + > + /* clear reset bit */ > + mtk_ddp_write_mask(&crc->cmdq_handle, 0, crc->cmdq_reg, 0, > + crc->rst_ofs, crc->rst_msk); > + > + /* jump to head of the cmdq packet */ > + cmdq_pkt_jump(&crc->cmdq_handle, crc->cmdq_handle.pa_base); > + > + return; > +cleanup: > + mtk_crtc_destroy_crc(crc); > +} > + > +/** > + * mtk_crtc_start_crc_cmdq - Start the GCE looping thread for CRC > update > + * @crc: Pointer of the CRC information > + */ > +void mtk_crtc_start_crc_cmdq(struct mtk_crtc_crc *crc) > +{ > + if (!crc->cmdq_client.chan) > + return; > + > + dma_sync_single_for_device(crc->cmdq_client.chan->mbox->dev, > + crc->cmdq_handle.pa_base, > + crc->cmdq_handle.cmd_buf_size, > + DMA_TO_DEVICE); > + mbox_send_message(crc->cmdq_client.chan, &crc->cmdq_handle); > + mbox_client_txdone(crc->cmdq_client.chan, 0); > +} > + > +/** > + * mtk_crtc_stop_crc_cmdq - Stop the GCE looping thread for CRC > update > + * @crc: Pointer of the CRC information > + */ > +void mtk_crtc_stop_crc_cmdq(struct mtk_crtc_crc *crc) > +{ > + if (!crc->cmdq_client.chan) > + return; > + > + /* remove all the commands from the cmdq packet */ > + mbox_flush(crc->cmdq_client.chan, 2000); > +} > +#endif > diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.h > b/drivers/gpu/drm/mediatek/mtk_crtc.h > index 388e900b6f4de..a79c4611754e4 100644 > --- a/drivers/gpu/drm/mediatek/mtk_crtc.h > +++ b/drivers/gpu/drm/mediatek/mtk_crtc.h > @@ -14,6 +14,34 @@ > #define MTK_MAX_BPC 10 > #define MTK_MIN_BPC 3 > > +/** > + * struct mtk_crtc_crc - crc related information > + * @ofs: register offset of crc > + * @rst_ofs: register offset of crc reset > + * @rst_msk: register mask of crc reset > + * @cnt: count of crc > + * @va: pointer to the start of crc array > + * @pa: physical address of the crc for gce to access > + * @cmdq_event: the event to trigger the cmdq > + * @cmdq_reg: address of the register that cmdq is going to access > + * @cmdq_client: handler to control cmdq (mbox channel, thread > ...etc.) > + * @cmdq_handle: cmdq packet to store the commands > + */ > +struct mtk_crtc_crc { > + const u32 *ofs; > + u32 rst_ofs; > + u32 rst_msk; > + size_t cnt; > + u32 *va; > +#if IS_REACHABLE(CONFIG_MTK_CMDQ) > + dma_addr_t pa; > + u32 cmdq_event; > + struct cmdq_client_reg *cmdq_reg; > + struct cmdq_client cmdq_client; > + struct cmdq_pkt cmdq_handle; > +#endif > +}; > + > void mtk_crtc_commit(struct drm_crtc *crtc); > int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int > *path, > unsigned int path_len, int priv_data_index, > @@ -25,4 +53,14 @@ void mtk_crtc_async_update(struct drm_crtc *crtc, > struct drm_plane *plane, > struct drm_atomic_state *plane_state); > struct device *mtk_crtc_dma_dev_get(struct drm_crtc *crtc); > > +void mtk_crtc_init_crc(struct mtk_crtc_crc *crc, const u32 > *crc_offset_table, > + size_t crc_count, u32 reset_offset, u32 > reset_mask); > +void mtk_crtc_read_crc(struct mtk_crtc_crc *crc, void __iomem *reg); > +void mtk_crtc_destroy_crc(struct mtk_crtc_crc *crc); > +#if IS_REACHABLE(CONFIG_MTK_CMDQ) > +void mtk_crtc_create_crc_cmdq(struct device *dev, struct > mtk_crtc_crc *crc); > +void mtk_crtc_start_crc_cmdq(struct mtk_crtc_crc *crc); > +void mtk_crtc_stop_crc_cmdq(struct mtk_crtc_crc *crc); > +#endif > + > #endif /* MTK_CRTC_H */ > diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h > b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h > index f7fe2e08dc8e2..b9c79e740abe0 100644 > --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h > @@ -88,6 +88,9 @@ struct mtk_ddp_comp_funcs { > void (*remove)(struct device *dev, struct mtk_mutex *mutex); > unsigned int (*encoder_index)(struct device *dev); > enum drm_mode_status (*mode_valid)(struct device *dev, const > struct drm_display_mode *mode); > + size_t (*crc_cnt)(struct device *dev); > + u32 *(*crc_entry)(struct device *dev); > + void (*crc_read)(struct device *dev); > }; > > struct mtk_ddp_comp { _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel