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Received: from DB9PR08MB6697.eurprd08.prod.outlook.com (2603:10a6:10:2ad::14) by PAWPR08MB9891.eurprd08.prod.outlook.com (2603:10a6:102:33b::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.292.25; Tue, 11 Aug 2026 19:43:56 +0000 Received: from DB9PR08MB6697.eurprd08.prod.outlook.com ([fe80::bdec:3e95:6614:441f]) by DB9PR08MB6697.eurprd08.prod.outlook.com ([fe80::bdec:3e95:6614:441f%6]) with mapi id 15.21.0315.012; Tue, 11 Aug 2026 19:43:56 +0000 Message-ID: <8e235c79-9b16-4f06-ba46-da7f28a2804a@genexis.eu> Date: Tue, 11 Aug 2026 21:43:54 +0200 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 0/2] PCI: mediatek-gen3: Add 2-lanes mode support + clock To: "Christian Marangi (Ansuel)" , Chen-Yu Tsai Cc: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Ryder Lee , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Jianjun Wang , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org References: <20260807152059.GA39821@bhelgaas> Content-Language: en-US From: Benjamin Larsson In-Reply-To: Content-Type: text/plain; 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On 10/08/2026 12:55, Christian Marangi (Ansuel) wrote: > Il giorno lun 10 ago 2026 alle ore 12:33 Chen-Yu Tsai > ha scritto: >> >> On Fri, Aug 7, 2026 at 11:21 PM Bjorn Helgaas wrote: >>> >>> On Fri, Aug 07, 2026 at 11:24:09AM +0800, Chen-Yu Tsai wrote: >>>> On Fri, Aug 7, 2026 at 12:53 AM Christian Marangi wrote: >>>>> This small series introduce support for 2-lanes mode for Airoha AN7581 >>>> >>>> Just a nitpick, but I would probably name this something else, like >>>> "cross-controller lane-bonding mode" or "lane stealing"? PCIe already >>>> has 2x lanes as a standard feature, so this naming is a bit confusing. >>>> It's not like dual-LVDS display in which LVDS is only a single lane. >>> >>> I suggested the "2-lane" and "x2" terminology because I assumed the >>> result is what the PCIe spec would describe as a "x2 Link" consisting >>> of two Lanes. >>> >>> If that's not the case, maybe "cross-controller lane-bonding mode" or >>> "lane stealing" would be more accurate, but I don't know what those >>> mean, so if we use them I would also like to know what the result >>> looks like in standard PCIe terms. >> >> Benjamin pointed out later in the thread that it is just bifurcation. >> > > Yes but as me, you, Benjamin and Bjorn people who weren't there with the HW > team at times the SoC was created, and given how the internal documentation > these are just assumption and observation... Everyone can be correct and wrong. > >> I would assume "PCIe bifurcation" is a standard term, so maybe we could >> call this "Support un-bifurcated 2-lane operation"? >> > > And how coming from PCIe bifurcation to un-bifurcated 2-lane operation keeps > the standard meaning? > > This terms is equally custom as the previous "cross-controller > lane-bonding mode" > and "lane stealing" > > I want to be honest... I'm not following why we are trying in every > way possible to find > a standard meaning for an highly integrated PCIe controller for a vendor SoC. > It's not like there are devices shipped with PCIe slot where you can > insert whatever > card you want. (there is only a single RFB board but that is really to > debug stuff and > develop) > > The SoC is designed to have WiFi cards attached and only a subset of them. > And some of them require 2 lanes mode to work with this special configuration. > > Even the DT bindings are not that specific to the details... at the > end of the day > everything is modelled as simple as "num-lanes = <2>;" > Hi, I agree with Christian here. The property num-lanes will be able to describe all possible pcie configurations of the AN7581 and AN7563 SoCs (the AN7563 is using the same pci controller if I understand things correctly). Adding more properties will not make it less complex. MvH Benjamin Larsson