From: Mark Brown <broonie@kernel.org>
To: Chi-Wen Weng <cwweng.linux@gmail.com>
Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
cwweng@nuvoton.com
Subject: Re: [PATCH v2 2/2] spi: ma35d1-qspi: Add Nuvoton MA35D1 QSPI controller support
Date: Mon, 8 Jun 2026 11:53:05 +0100 [thread overview]
Message-ID: <8e751df3-6237-4c8e-9c87-34bb67e435f7@sirena.org.uk> (raw)
In-Reply-To: <20260608025009.1504971-3-cwweng@nuvoton.com>
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On Mon, Jun 08, 2026 at 10:50:09AM +0800, Chi-Wen Weng wrote:
> Add SPI controller driver support for the Nuvoton MA35D1 Quad SPI
> controller.
> +static void nuvoton_qspi_mem_set_cs(struct spi_device *spi, bool enable)
> +{
> + struct nuvoton_qspi *qspi = spi_controller_get_devdata(spi->controller);
> + bool assert = enable;
> +
> + if (spi->mode & SPI_CS_HIGH)
> + assert = !assert;
Hrm, we should have the core deal with this. Separate issue though.
> + ctlr->num_chipselect = NUVOTON_QSPI_DEFAULT_NUM_CS;
> + ctlr->mem_ops = &nuvoton_qspi_mem_ops;
We don't specify mem_caps, I'm vaugely surprised nothing trips over that
when testing.
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next prev parent reply other threads:[~2026-06-08 10:53 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-08 2:50 [PATCH v2 0/2] spi: ma35d1-qspi: Add Nuvoton MA35D1 QSPI controller Chi-Wen Weng
2026-06-08 2:50 ` [PATCH v2 1/2] dt-bindings: spi: nuvoton,ma35d1-qspi: Add Nuvoton MA35D1 QSPI Chi-Wen Weng
2026-06-08 10:02 ` Krzysztof Kozlowski
2026-06-08 11:41 ` Chi-Wen Weng
2026-06-08 2:50 ` [PATCH v2 2/2] spi: ma35d1-qspi: Add Nuvoton MA35D1 QSPI controller support Chi-Wen Weng
2026-06-08 10:53 ` Mark Brown [this message]
2026-06-08 11:45 ` Chi-Wen Weng
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