From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 49FB8C433EF for ; Mon, 29 Nov 2021 22:55:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=T+crMprlw2z5AV1ovmZp7JxbG9D1Af0ti0SjVsVEmfs=; b=KqbDzqidOaALRs kuHRoO21MZEj56iDitombbwCMrPnZEsj5WGZaK9G38BWv1OXu0kLNQqXvOtUo9apVivKUTvFsByKR dm9fy47DUgm5yLI3dEGzVCu44sAeYx86ppb8SuovMc+2H1kRfwV44kgwiTBJ6fXiKxtWp1XoMaq6m kOMh0XbytRv1QLKU1lM2WBSB4x3SjJuDOv93/G97Vton5mnIY8QQCmG59HkmHgvP4HihNaqCtQlnG g++hKZVnx13OqBdcEM66Oe56RFR2o4u5C1BUOvn9qyQfYr0xnh3e6VHyHeIBEVOHh11XWsuSKO2Md Jn5akDgkMADjNe0cOBzQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mrpWw-002zNG-6f; Mon, 29 Nov 2021 22:53:50 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mrpWs-002zMV-5r for linux-arm-kernel@lists.infradead.org; Mon, 29 Nov 2021 22:53:47 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4375C1063; Mon, 29 Nov 2021 14:53:44 -0800 (PST) Received: from [10.57.34.182] (unknown [10.57.34.182]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C8E633F5A1; Mon, 29 Nov 2021 14:53:42 -0800 (PST) Message-ID: <8ea071d7-a8ff-813a-6268-7445dbbf0c1a@arm.com> Date: Mon, 29 Nov 2021 22:53:37 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; rv:91.0) Gecko/20100101 Thunderbird/91.3.2 Subject: Re: [PATCH 2/2] arm64: tegra: Describe Tegra234 CPU hierarchy Content-Language: en-GB To: Rob Herring , Thierry Reding Cc: Jon Hunter , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, Mark Rutland , Will Deacon References: <20211112131904.3683428-1-thierry.reding@gmail.com> <20211112131904.3683428-2-thierry.reding@gmail.com> From: Robin Murphy In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211129_145346_304169_56DF48D2 X-CRM114-Status: GOOD ( 15.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2021-11-29 21:06, Rob Herring wrote: > On Fri, Nov 12, 2021 at 02:19:04PM +0100, Thierry Reding wrote: >> From: Thierry Reding >> >> The NVIDIA Tegra234 SoC has 3 clusters of 4 Cortex-A78AE CPU cores each, >> for a total of 12 CPUs. Each CPU has 64 KiB instruction and data caches >> with each cluster having an additional 256 KiB unified L2 cache and a 2 >> MiB L3 cache. >> >> Signed-off-by: Thierry Reding >> --- >> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 365 ++++++++++++++++++++++- >> 1 file changed, 363 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi >> index 104e5fdd5f8a..db24f48edc9f 100644 >> --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi >> +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi >> @@ -736,12 +736,373 @@ cpus { >> #address-cells = <1>; >> #size-cells = <0>; >> >> - cpu@0 { >> + cpu0_0: cpu@0 { >> + compatible = "arm,cortex-a78"; >> device_type = "cpu"; >> - reg = <0x000>; >> + reg = <0x00000>; >> >> enable-method = "psci"; >> + > >> + i-cache-size = <65536>; >> + i-cache-line-size = <64>; >> + i-cache-sets = <256>; >> + d-cache-size = <65536>; >> + d-cache-line-size = <64>; >> + d-cache-sets = <256>; > > Isn't all this discoverable? No. The required parameters for cache maintenance by set/way are discoverable from the CTR, and if you're particularly lucky they might even happen to reflect the underlying physical cache structures, but there's absolutely no guarantee of that, and there definitely exist cases where they don't. [...] >> + pmu { >> + compatible = "arm,armv8-pmuv3"; Oh, I'd missed this - per the current state of things, we should really have a proper compatible for the PMU as well. (Suggestions for ways to improve the current state of things for better forward- and backward- compatibility welcome - I started having a mad idea about autogenerating a PMU name from the CPU compatible if the generic PMU compatible is present, but I'm not sure that's realistic). Robin. >> + interrupts = ; >> + status = "okay"; > > That's the default. > >> }; >> >> psci { >> -- >> 2.33.1 >> >> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel