* [PATCH] ARM: dts: vexpress: Support GICC_DIR operations
@ 2016-12-10 20:13 Christoffer Dall
2016-12-12 17:35 ` Marc Zyngier
0 siblings, 1 reply; 4+ messages in thread
From: Christoffer Dall @ 2016-12-10 20:13 UTC (permalink / raw)
To: linux-arm-kernel
The GICv2 CPU interface registers span across 8K, not 4K as indicated in
the DT. Only the GICC_DIR register is located after the initial 4K
boundary, leaving a functional system but without support for separately
EOI'ing and deactivating interrupts.
After this change the system support split priority drop and interrupt
deactivation.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 0205c97..2e0cf39 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -126,7 +126,7 @@
#address-cells = <0>;
interrupt-controller;
reg = <0 0x2c001000 0 0x1000>,
- <0 0x2c002000 0 0x1000>,
+ <0 0x2c002000 0 0x2000>,
<0 0x2c004000 0 0x2000>,
<0 0x2c006000 0 0x2000>;
interrupts = <1 9 0xf04>;
--
2.9.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH] ARM: dts: vexpress: Support GICC_DIR operations
2016-12-10 20:13 [PATCH] ARM: dts: vexpress: Support GICC_DIR operations Christoffer Dall
@ 2016-12-12 17:35 ` Marc Zyngier
2016-12-13 12:16 ` Sudeep Holla
0 siblings, 1 reply; 4+ messages in thread
From: Marc Zyngier @ 2016-12-12 17:35 UTC (permalink / raw)
To: linux-arm-kernel
[+Sudeep]
On 10/12/16 20:13, Christoffer Dall wrote:
> The GICv2 CPU interface registers span across 8K, not 4K as indicated in
> the DT. Only the GICC_DIR register is located after the initial 4K
> boundary, leaving a functional system but without support for separately
> EOI'ing and deactivating interrupts.
>
> After this change the system support split priority drop and interrupt
> deactivation.
>
> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
> ---
> arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
> index 0205c97..2e0cf39 100644
> --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
> +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
> @@ -126,7 +126,7 @@
> #address-cells = <0>;
> interrupt-controller;
> reg = <0 0x2c001000 0 0x1000>,
> - <0 0x2c002000 0 0x1000>,
> + <0 0x2c002000 0 0x2000>,
> <0 0x2c004000 0 0x2000>,
> <0 0x2c006000 0 0x2000>;
> interrupts = <1 9 0xf04>;
>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] ARM: dts: vexpress: Support GICC_DIR operations
2016-12-12 17:35 ` Marc Zyngier
@ 2016-12-13 12:16 ` Sudeep Holla
2016-12-13 13:00 ` Marc Zyngier
0 siblings, 1 reply; 4+ messages in thread
From: Sudeep Holla @ 2016-12-13 12:16 UTC (permalink / raw)
To: linux-arm-kernel
On 12/12/16 17:35, Marc Zyngier wrote:
> [+Sudeep]
>
> On 10/12/16 20:13, Christoffer Dall wrote:
>> The GICv2 CPU interface registers span across 8K, not 4K as indicated in
>> the DT. Only the GICC_DIR register is located after the initial 4K
>> boundary, leaving a functional system but without support for separately
>> EOI'ing and deactivating interrupts.
>>
>> After this change the system support split priority drop and interrupt
>> deactivation.
>>
>> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
>> ---
>> arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
>> index 0205c97..2e0cf39 100644
>> --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
>> +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
>> @@ -126,7 +126,7 @@
>> #address-cells = <0>;
>> interrupt-controller;
>> reg = <0 0x2c001000 0 0x1000>,
>> - <0 0x2c002000 0 0x1000>,
>> + <0 0x2c002000 0 0x2000>,
>> <0 0x2c004000 0 0x2000>,
>> <0 0x2c006000 0 0x2000>;
>> interrupts = <1 9 0xf04>;
>>
>
> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
>
Thanks Marc, I see couple of other instances of this like tc2 and rtsm
model on arm64. Do they need to be fixed too ? I guess so. If so I will
fixup this to patch add tc1. And add another one for rtsm.
Also I see loads of gic-400 compatible dts(mainly rockchip and renasas)
having just 4k. Are they left like this intentionally ? I remember you
fixing most of the DTS when you found this issue initially.
--
Regards,
Sudeep
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] ARM: dts: vexpress: Support GICC_DIR operations
2016-12-13 12:16 ` Sudeep Holla
@ 2016-12-13 13:00 ` Marc Zyngier
0 siblings, 0 replies; 4+ messages in thread
From: Marc Zyngier @ 2016-12-13 13:00 UTC (permalink / raw)
To: linux-arm-kernel
On 13/12/16 12:16, Sudeep Holla wrote:
>
>
> On 12/12/16 17:35, Marc Zyngier wrote:
>> [+Sudeep]
>>
>> On 10/12/16 20:13, Christoffer Dall wrote:
>>> The GICv2 CPU interface registers span across 8K, not 4K as indicated in
>>> the DT. Only the GICC_DIR register is located after the initial 4K
>>> boundary, leaving a functional system but without support for separately
>>> EOI'ing and deactivating interrupts.
>>>
>>> After this change the system support split priority drop and interrupt
>>> deactivation.
>>>
>>> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
>>> ---
>>> arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
>>> index 0205c97..2e0cf39 100644
>>> --- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
>>> +++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
>>> @@ -126,7 +126,7 @@
>>> #address-cells = <0>;
>>> interrupt-controller;
>>> reg = <0 0x2c001000 0 0x1000>,
>>> - <0 0x2c002000 0 0x1000>,
>>> + <0 0x2c002000 0 0x2000>,
>>> <0 0x2c004000 0 0x2000>,
>>> <0 0x2c006000 0 0x2000>;
>>> interrupts = <1 9 0xf04>;
>>>
>>
>> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
>>
>
> Thanks Marc, I see couple of other instances of this like tc2 and rtsm
> model on arm64. Do they need to be fixed too ? I guess so. If so I will
> fixup this to patch add tc1. And add another one for rtsm.
Yes, that'd be good.
> Also I see loads of gic-400 compatible dts(mainly rockchip and renasas)
> having just 4k. Are they left like this intentionally ? I remember you
> fixing most of the DTS when you found this issue initially.
I still have these patches stashed somewhere (I remember sunxi being one
of the offender as well). I also need to come up with a software
workaround enabling the 8kB region with the old DT (because it is likely
that KVM will stop working on them if we merge Christoffer's timer patches).
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply [flat|nested] 4+ messages in thread
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2016-12-10 20:13 [PATCH] ARM: dts: vexpress: Support GICC_DIR operations Christoffer Dall
2016-12-12 17:35 ` Marc Zyngier
2016-12-13 12:16 ` Sudeep Holla
2016-12-13 13:00 ` Marc Zyngier
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