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[89.212.118.115]) by smtp.gmail.com with ESMTPSA id h3-20020a1709066d8300b0074136cac2e7sm1941855ejt.81.2022.11.06.02.16.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 02:16:30 -0800 (PST) From: Jernej =?utf-8?B?xaBrcmFiZWM=?= To: Samuel Holland , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , Andre Przywara Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, soc@kernel.org, Icenowy Zheng , =?ISO-8859-1?Q?Cl=E9ment_P=E9ron?= Subject: Re: [PATCH 3/3] ARM: dts: suniv: Add Lctech Pi F1C200s devicetree Date: Sun, 06 Nov 2022 11:16:29 +0100 Message-ID: <9064733.rMLUfLXkoz@jernej-laptop> In-Reply-To: <20221025145909.2837939-4-andre.przywara@arm.com> References: <20221025145909.2837939-1-andre.przywara@arm.com> <20221025145909.2837939-4-andre.przywara@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221106_021635_519035_E436B90F X-CRM114-Status: GOOD ( 25.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Andre, sorry for late review. Dne torek, 25. oktober 2022 ob 16:59:09 CET je Andre Przywara napisal(a): > The Lctech Pi F1C200s (also previously known under the Cherry Pi brand) > is a small development board with the Allwinner F1C200s SoC. This is the > same as the F1C100s, but with 64MB instead of 32MB co-packaged DRAM. > > Alongside the obligatory micro-SD card slot, the board features a > SPI-NAND flash chip, LCD and touch connectors, and unpopulated > expansion header pins. > There are two USB Type-C ports on the board: One supplies the power, also > connects to the USB MUSB OTG controller port. The other one is connected > to an CH340 USB serial chip, which in turn is connected to UART1. > > Add a devicetree file, so that the board can be used easily. > > Signed-off-by: Andre Przywara > --- > arch/arm/boot/dts/Makefile | 1 + > arch/arm/boot/dts/suniv-f1c100s.dtsi | 5 ++ > arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts | 80 +++++++++++++++++++ > 3 files changed, 86 insertions(+) > create mode 100644 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts > > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 6abf6434eb372..f99c5c20bf7ef 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -1394,6 +1394,7 @@ dtb-$(CONFIG_MACH_SUN9I) += \ > sun9i-a80-cubieboard4.dtb > dtb-$(CONFIG_MACH_SUNIV) += \ > suniv-f1c100s-licheepi-nano.dtb \ > + suniv-f1c200s-lctech-pi.dtb \ > suniv-f1c200s-popstick-v1.1.dtb > dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ > tegra20-acer-a500-picasso.dtb \ > diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi > b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 0f24c766c9fc5..2ec022e92eea8 > 100644 > --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi > +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi > @@ -201,6 +201,11 @@ uart0_pe_pins: uart0-pe-pins { > pins = "PE0", "PE1"; > function = "uart0"; > }; > + > + uart1_pa_pins: uart1-pa-pins { > + pins = "PA2", "PA3"; > + function = "uart1"; > + }; /omit-if-no-ref/ > }; > > timer@1c20c00 { > diff --git a/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts > b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts new file mode 100644 > index 0000000000000..a9d1778395438 > --- /dev/null > +++ b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts > @@ -0,0 +1,80 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright 2022 Arm Ltd, > + * based on work: > + * Copyright 2022 Icenowy Zheng > + */ > + > +/dts-v1/; > +#include "suniv-f1c100s.dtsi" > + > +#include > + > +/ { > + model = "Lctech Pi F1C200s"; > + compatible = "lctech,pi-f1c200s", "allwinner,suniv-f1c200s", > + "allwinner,suniv-f1c100s"; > + > + aliases { > + mmc0 = &mmc0; > + serial0 = &uart1; > + spi0 = &spi0; We don't do aliases for mmc nor spi. Best regards, Jernej > + }; > + > + chosen { > + stdout-path = "serial0:115200n8"; > + }; > + > + reg_vcc3v3: regulator-3v3 { > + compatible = "regulator-fixed"; > + regulator-name = "vcc3v3"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + }; > +}; > + > +&mmc0 { > + broken-cd; > + bus-width = <4>; > + disable-wp; > + vmmc-supply = <®_vcc3v3>; > + status = "okay"; > +}; > + > +&otg_sram { > + status = "okay"; > +}; > + > +&spi0 { > + pinctrl-names = "default"; > + pinctrl-0 = <&spi0_pc_pins>; > + status = "okay"; > + > + flash@0 { > + compatible = "spi-nand"; > + reg = <0>; > + #address-cells = <1>; > + #size-cells = <1>; > + spi-max-frequency = <40000000>; > + }; > +}; > + > +&uart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&uart1_pa_pins>; > + status = "okay"; > +}; > + > +/* > + * This is a Type-C socket, but CC1/2 are not connected, and VBUS is > connected + * to Vin, which supplies the board. Host mode works (if the > board is powered + * otherwise), but peripheral is probably the intention. > + */ > +&usb_otg { > + dr_mode = "peripheral"; > + status = "okay"; > +}; > + > +&usbphy { > + status = "okay"; > +}; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel