Re: [PATCH RESEND v3 2/3] clk: en7523: Add reset-controller support for EN7523 SoC

[Philipp Zabel <p.zabel@pengutronix.de>]

On Mo, 2025-11-10 at 06:56 +0300, Mikhail Kshevetskiy wrote:
> Introduce reset API support to EN7523 clock driver. EN7523 uses the
> same reset logic as EN7581, so just reuse existing code.
> 
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>

> ---
>  drivers/clk/clk-en7523.c | 64 ++++++++++++++++++++++++++++++++++++----
>  1 file changed, 59 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
> index 15bbdeb60b8e..08cc8e5acf43 100644
> --- a/drivers/clk/clk-en7523.c
> +++ b/drivers/clk/clk-en7523.c
> @@ -9,6 +9,7 @@
>  #include <linux/regmap.h>
>  #include <linux/reset-controller.h>
>  #include <dt-bindings/clock/en7523-clk.h>
> +#include <dt-bindings/reset/airoha,en7523-reset.h>
>  #include <dt-bindings/reset/airoha,en7581-reset.h>
>  
>  #define RST_NR_PER_BANK			32
> @@ -299,6 +300,53 @@ static const u16 en7581_rst_ofs[] = {
>  	REG_RST_CTRL1,
>  };
>  
> +static const u16 en7523_rst_map[] = {
> +	/* RST_CTRL2 */
> +	[EN7523_XPON_PHY_RST]		= 0,
> +	[EN7523_XSI_MAC_RST]		= 7,
> +	[EN7523_XSI_PHY_RST]		= 8,
> +	[EN7523_NPU_RST]		= 9,
> +	[EN7523_I2S_RST]		= 10,
> +	[EN7523_TRNG_RST]		= 11,
> +	[EN7523_TRNG_MSTART_RST]	= 12,
> +	[EN7523_DUAL_HSI0_RST]		= 13,
> +	[EN7523_DUAL_HSI1_RST]		= 14,
> +	[EN7523_HSI_RST]		= 15,
> +	[EN7523_DUAL_HSI0_MAC_RST]	= 16,
> +	[EN7523_DUAL_HSI1_MAC_RST]	= 17,
> +	[EN7523_HSI_MAC_RST]		= 18,
> +	[EN7523_WDMA_RST]		= 19,
> +	[EN7523_WOE0_RST]		= 20,
> +	[EN7523_WOE1_RST]		= 21,
> +	[EN7523_HSDMA_RST]		= 22,
> +	[EN7523_I2C2RBUS_RST]		= 23,
> +	[EN7523_TDMA_RST]		= 24,
> +	/* RST_CTRL1 */
> +	[EN7523_PCM1_ZSI_ISI_RST]	= RST_NR_PER_BANK + 0,
> +	[EN7523_FE_PDMA_RST]		= RST_NR_PER_BANK + 1,
> +	[EN7523_FE_QDMA_RST]		= RST_NR_PER_BANK + 2,
> +	[EN7523_PCM_SPIWP_RST]		= RST_NR_PER_BANK + 4,
> +	[EN7523_CRYPTO_RST]		= RST_NR_PER_BANK + 6,
> +	[EN7523_TIMER_RST]		= RST_NR_PER_BANK + 8,
> +	[EN7523_PCM1_RST]		= RST_NR_PER_BANK + 11,
> +	[EN7523_UART_RST]		= RST_NR_PER_BANK + 12,
> +	[EN7523_GPIO_RST]		= RST_NR_PER_BANK + 13,
> +	[EN7523_GDMA_RST]		= RST_NR_PER_BANK + 14,
> +	[EN7523_I2C_MASTER_RST]		= RST_NR_PER_BANK + 16,
> +	[EN7523_PCM2_ZSI_ISI_RST]	= RST_NR_PER_BANK + 17,
> +	[EN7523_SFC_RST]		= RST_NR_PER_BANK + 18,
> +	[EN7523_UART2_RST]		= RST_NR_PER_BANK + 19,
> +	[EN7523_GDMP_RST]		= RST_NR_PER_BANK + 20,
> +	[EN7523_FE_RST]			= RST_NR_PER_BANK + 21,
> +	[EN7523_USB_HOST_P0_RST]	= RST_NR_PER_BANK + 22,
> +	[EN7523_GSW_RST]		= RST_NR_PER_BANK + 23,
> +	[EN7523_SFC2_PCM_RST]		= RST_NR_PER_BANK + 25,
> +	[EN7523_PCIE0_RST]		= RST_NR_PER_BANK + 26,
> +	[EN7523_PCIE1_RST]		= RST_NR_PER_BANK + 27,
> +	[EN7523_PCIE_HB_RST]		= RST_NR_PER_BANK + 29,
> +	[EN7523_XPON_MAC_RST]		= RST_NR_PER_BANK + 31,
> +};
> +
>  static const u16 en7581_rst_map[] = {
>  	/* RST_CTRL2 */
>  	[EN7581_XPON_PHY_RST]		= 0,
> @@ -357,6 +405,9 @@ static const u16 en7581_rst_map[] = {
>  	[EN7581_XPON_MAC_RST]		= RST_NR_PER_BANK + 31,
>  };
>  
> +static int en7581_reset_register(struct device *dev, void __iomem *base,
> +				 const u16 *rst_map, int nr_resets);
> +
>  static u32 en7523_get_base_rate(const struct en_clk_desc *desc, u32 val)
>  {
>  	if (!desc->base_bits)
> @@ -552,7 +603,8 @@ static int en7523_clk_hw_init(struct platform_device *pdev,
>  
>  	en7523_register_clocks(&pdev->dev, clk_data, base, np_base);
>  
> -	return 0;
> +	return en7581_reset_register(&pdev->dev, np_base, en7523_rst_map,
> +				     ARRAY_SIZE(en7523_rst_map));

I wonder if this wouldn't be better moved out of hw_init(), with
rst_map and the corresponding ARRAY_SIZE() stored in struct
en_clk_soc_data. Registering a reset controller is not hardware
initialization, after all. But that's not an issue with this patch.

regards
Philipp