From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 50ABAC3DA49 for ; Fri, 26 Jul 2024 07:13:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=FRhgwFDe2a/nf9wD17fnaE3wcTkqmxJhzhSenB8Q4oI=; b=sfJR5whiIxj+mOYY1BO/YdL8aR p7DVLXOYTwWi67PblNonM5g0Iptc0Xkgl4bQBIeUO4ZOdbvjQApwxPqli62iMIJPdiDr1UicY6hqr Tgz2YKtnfyJc5ZG32885qCFKcrEwuxtP7yuLT2ycsLQqttblBDqKvCauYSCwDOWvT7YQqtvRjrwTU mV5P0Wpxy47Yk856Wn0Da0FqlnSdidnSkpxMkmxbhQjOS3kGASAOL5j/6OaDs7cCN/Q+EagoBaM7N G+fXFVVFpIBywjPU7mfe5DU+Q92DKs7fQImndiH4Fk/R5iVbkKfgmuBLcJTDU+D30MOe6OPyTpriZ G9Wmuh/g==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sXF8B-000000038i5-05tY; Fri, 26 Jul 2024 07:12:47 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1sXF7m-000000038ft-2MHk for linux-arm-kernel@lists.infradead.org; Fri, 26 Jul 2024 07:12:24 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DDBD91007; Fri, 26 Jul 2024 00:12:46 -0700 (PDT) Received: from [10.163.53.239] (unknown [10.163.53.239]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D34453F73F; Fri, 26 Jul 2024 00:12:19 -0700 (PDT) Message-ID: <917eec83-1ab2-4a90-bb2d-2c5b1196e9e8@arm.com> Date: Fri, 26 Jul 2024 12:42:15 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [boot-wrapper 1/3] aarch64: Enable access into 128 bit system registers from EL2 and below To: Mark Rutland Cc: linux-arm-kernel@lists.infradead.org References: <20240723110630.483871-1-anshuman.khandual@arm.com> <20240723110630.483871-2-anshuman.khandual@arm.com> Content-Language: en-US From: Anshuman Khandual In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240726_001222_679933_E19A1BD6 X-CRM114-Status: GOOD ( 14.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 7/25/24 14:14, Mark Rutland wrote: > On Tue, Jul 23, 2024 at 04:36:28PM +0530, Anshuman Khandual wrote: >> FEAT_D128 adds 128 bit system registers like PAR_EL1, TTBR0_EL1, TTBR1_EL1, >> TTBR0_EL2, TTBR1_EL2, TTBR0_EL12, TTBR1_EL12 , VTTBR_EL2, RCWMASK_EL1, and >> RCWSMASK_EL1. But access into these register from EL2 and below trap to EL3 >> unless SCR_EL3.D128En is set. > > Do we need to initialize any of these new bits, or do they have no > effect on a lower EL unless explicitly opted-in at that lower EL? Unlike SCTRL2_EL1/EL2, these are actual end use registers for the lower EL and only available in 128 bit width format when FEAT_D128 is both implemented and opted in. > > Otherwise this looks superficially fine, but it should come after > enabling SCTLR2. Sure, will moved it after SCTLR2 patch. > > Mark. > >> >> Enable access to 128 bit registers when they are implemented. >> >> Signed-off-by: Anshuman Khandual >> --- >> arch/aarch64/include/asm/cpu.h | 2 ++ >> arch/aarch64/init.c | 3 +++ >> 2 files changed, 5 insertions(+) >> >> diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h >> index 124ef91..0b8b463 100644 >> --- a/arch/aarch64/include/asm/cpu.h >> +++ b/arch/aarch64/include/asm/cpu.h >> @@ -57,6 +57,7 @@ >> #define SCR_EL3_EnTP2 BIT(41) >> #define SCR_EL3_TCR2EN BIT(43) >> #define SCR_EL3_PIEN BIT(45) >> +#define SCR_EL3_D128En BIT(47) >> >> #define HCR_EL2_RES1 BIT(1) >> >> @@ -85,6 +86,7 @@ >> #define ID_AA64MMFR3_EL1_S2PIE BITS(15, 12) >> #define ID_AA64MMFR3_EL1_S1POE BITS(19, 16) >> #define ID_AA64MMFR3_EL1_S2POE BITS(23, 20) >> +#define ID_AA64MMFR3_EL1_D128 BITS(35, 32) >> >> #define ID_AA64PFR1_EL1_MTE BITS(11, 8) >> #define ID_AA64PFR1_EL1_SME BITS(27, 24) >> diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c >> index 37cb45f..7d9d0d9 100644 >> --- a/arch/aarch64/init.c >> +++ b/arch/aarch64/init.c >> @@ -89,6 +89,9 @@ void cpu_init_el3(void) >> if (!kernel_is_32bit()) >> scr |= SCR_EL3_RW; >> >> + if (mrs_field(ID_AA64MMFR3_EL1, D128)) >> + scr |= SCR_EL3_D128En; >> + >> msr(SCR_EL3, scr); >> >> msr(CPTR_EL3, cptr); >> -- >> 2.25.1 >>