From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A259FE7D0C2 for ; Fri, 22 Sep 2023 04:17:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Date:Cc:To:From:Subject:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=AX4a55Cv/51lk0aztjS7USI6IMOEZ+jwIthG2S0C0Lg=; b=wZSY3RTk9BTlNP qc4NzWdT0/cBZ0ss01ZZtgPGFUxfmgaS/H7XBdMUkSWaS6Ur5lgpIu33RZN5CPyYdSEbdk7QB1Eiv P6ZxswDXxDx5Qw128uvPO6BBOF70TSFYiOul7NS1yempPpILKjoTXOY7nvldl3pYWsrsebK4+NqD7 nj0dpB+iV9mKDXupqoCnWT1Wa1ZQIOKdBi9ZCph8VPbE0yywo9LC/DUoTbrHB5/8kWmJnJ8C7J34d YaGyurenirenbcW+OA8WZkGla/jHdoIvejCMfLi/cv5/ogaGXsR8v/oBOVu4odnUEL9xYbhKpjAXY PYcvNtOuZujb595RchAg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qjXbL-007n5l-32; Fri, 22 Sep 2023 04:17:11 +0000 Received: from pi.codeconstruct.com.au ([203.29.241.158] helo=codeconstruct.com.au) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1qjXbJ-007n4V-0M for linux-arm-kernel@lists.infradead.org; Fri, 22 Sep 2023 04:17:10 +0000 Received: from [192.168.68.112] (ppp14-2-88-115.adl-apt-pir-bras31.tpg.internode.on.net [14.2.88.115]) by mail.codeconstruct.com.au (Postfix) with ESMTPSA id 12076201B9; Fri, 22 Sep 2023 12:16:51 +0800 (AWST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=codeconstruct.com.au; s=2022a; t=1695356217; bh=Qb0gRj6pnqlTclpvVQaaCBr09PUiG9zueH5w8ndfnhk=; h=Subject:From:To:Cc:Date:In-Reply-To:References; b=Hg/jnYstvcPUnQYL7gXd43PHO+Cy5vuOCBxTd3C/au0t02Z1QLZB+yiTYoG2IkuU4 9JIDRFmpJFTDDJbnKB0iO9xFWyWSq2WHirAma7WtkuA+6Io3MT/IbRHkmuvyvxScR8 RO4T/44rfsOv7adGIcwkYeFZmfdGTSn2rUJxOW4AfDTlVOuqIkS8/AGFFaahnfUUb9 /gyrPVeacfZahfQjrvco1R1ztvzSD/4kyBAmsl+mm2+rCoeRnFn+8oTiRoGR0uCI6C 7gD5p0XannjiyPhnwVJCE0TLzPQ2GT466QgZZRhzuyo5WTV31Z5g8RZc7inBxDDLJ9 H7/7om750V2PQ== Message-ID: <91be26169ebbddf3c05cd19626478246cb72a72a.camel@codeconstruct.com.au> Subject: Re: [PATCH] watchdog: aspeed: Add sysfs attributes for reset mask bits From: Andrew Jeffery To: Zev Weiss , Wim Van Sebroeck , Guenter Roeck , Joel Stanley , Andrew Jeffery Cc: linux-watchdog@vger.kernel.org, linux-aspeed@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, openbmc@lists.ozlabs.org, Thomas =?ISO-8859-1?Q?Wei=DFschuh?= , Eddie James , Ivan Mikhaylov Date: Fri, 22 Sep 2023 13:46:50 +0930 In-Reply-To: <20230922013542.29136-2-zev@bewilderbeest.net> References: <20230922013542.29136-2-zev@bewilderbeest.net> User-Agent: Evolution 3.46.4-2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230921_211709_369033_B9795BAC X-CRM114-Status: GOOD ( 14.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 2023-09-21 at 18:35 -0700, Zev Weiss wrote: > The AST2500 and AST2600 watchdog timers provide the ability to control > which devices are reset by the watchdog timer via a reset mask > resgister. Previously the driver ignored that register, leaving > whatever configuration it found at boot and offering no way of > altering its settings. Add a 'reset_ctrl' sysfs subdirectory with a > file per bit so that userspace can determine which devices the reset > is applied to. > > Note that not all bits in the hardware register are exposed -- in > particular, the ARM CPU and SOC/misc reset bits are left hidden since > clearing them can render the system unable to reboot. > > Signed-off-by: Zev Weiss > --- > > I'm porting OpenBMC to a platform that requires that the LPC controller remain > un-reset by a BMC reboot. With this patch userspace can control the reset > mask of the Aspeed watchdog timer, with a few bits remaining unexposed so as > to prevent some almost-certainly undesirable situations. If there are other > bits that people feel shouldn't be exposed (or conversely if someone feels > strongly that the "dangerous" bits _should_ be exposed) I can adjust > accordingly. Is there a reason this has to be managed by userspace? It sounds a lot like a property of platform design, in which case exposing this feature in the devicetree might be a better approach. Andrew _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel