From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41FA8C433F5 for ; Tue, 5 Apr 2022 15:44:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Content-ID:In-Reply-To: References:Message-ID:Date:Subject:CC:To:From:Reply-To:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=e17S09oYlcIMvlwSYNBp/VyVBbgvX4MTlA6/WLmnuMk=; b=kvehHQQnWL7ahu MY/nKvvz2tVNnT4HGvhMtWGJaw0B5ULg2J7KkiW8lea+1WlUpjDR//qtGSQf0pipajfT6dtEagQVb 2UD0JjMyFOQAwJri2ynN8TtMDZnnz+r0wRplXdTNUo5VONQgnSM6iuStDxkVqcGDRWlYkRL2HQmZf kEEJxxfo6J+zLlqJLYng/swOpuxgdEAcM84VDgSucZrpgZasrOZLW0FeQ+YwkYP29DOlZXmnSIM0L Py5n5IYCZBYyhyHdb9ce69pakiCiHgYSHfxTHJkafow2i6sqSLCCRcib0banG4v/nfYQt+VpP5OIJ HwvvjU86ol7xmFSMMZQQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nblKd-001l2e-RT; Tue, 05 Apr 2022 15:43:00 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nblKa-001l1k-Qe for linux-arm-kernel@lists.infradead.org; Tue, 05 Apr 2022 15:42:58 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1649173376; x=1680709376; h=from:to:cc:subject:date:message-id:references: in-reply-to:content-id:content-transfer-encoding: mime-version; bh=vGmj3Y0IIlIk6gpSt2hVgAmDTIyd+PehJrs89VgsB3E=; b=zh2xk9tRdaHkAVTJ9azz6n0hKR2ullGmeXRCJkY/uzj9strvUv9NeZ2Y 6HmgrlnYm5TbK+bv7XqjflqlcUM2X7bBwSeeON82bNBw5qIXHrTHr3xie MYTnHYhyiPCTsAg7diJ/5+9IjhJPstHijGQHiasvVSj9jxNlhne8HDgSO Vk3pw0mZl4LYhBFvI4o1NU0wTd5Aa+bAbwCIHADupNvUodOmx3zg/V5SE WWrGmceCIs+hI7n/r0cmzm8AJz82UxcTNVUIiv+T7nDq/we8cpc0sFLUa 0vxrwwS0ctm47BruFx074AxQwfqCc8Mcu3Yvdx/cQ0M95tR6/LUh/GErT w==; X-IronPort-AV: E=Sophos;i="5.90,236,1643698800"; d="scan'208";a="159389694" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 05 Apr 2022 08:42:55 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Tue, 5 Apr 2022 08:42:55 -0700 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (10.10.215.89) by email.microchip.com (10.10.87.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17 via Frontend Transport; Tue, 5 Apr 2022 08:42:54 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=hctkqS8dOVylk5WGHDJJ3USdl2MozYp92SaQih0FIZk4GF+tq9YPnPiM+rzXUuEYeuelHdQBcPg6yUTzGlv0PbVZiKL29YEFHR/9YSaP8M5AlFlVLUp1KL09gpkVZ3PQyF4otPbl65XbIHY6+YwNTgrhfBaw6caGo9v5vKhCTudulHBj0Ozr9opZkSqjqTiF/kGhBULuHZ/YrZL2kYLyOg4neaLPaizGnSt4O1ZDMk9OT5ZKCQZUKkI0ji7y4JuI6C3gJRmlQOy1rfLrOcX8sljwXCRHZ82+mY0gIyH7oW5zNSmsIDam8VmNB7Fi3jbyA6oH7z6j3Hw/Wp4mZF2tRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=vGmj3Y0IIlIk6gpSt2hVgAmDTIyd+PehJrs89VgsB3E=; b=ZClHL7tmtYVZrcphAPTiWl09ZzluL0cc5B9rtyZsJGi1k1v7trPo+eqLWTI4zsccNDJg/D4iKz6utV14WgPyiLWDQegjwkpiHv07H4vGOuxHaHH6SPXB/kqaqZGtifSdgaOk5hDvRhgIiSlmp2gT+osFKdOc7oumuCCHrnNVpToF3uTmNyc3cjEiMz25XYpJ608sSPy4SR4zRUXsZiWuIrU8MD/LkbSkJ9MzZnVw+fa+T2Jkuu8NXC+wr61p+caiwFhA0itXyK3t8eQ8dAt1DeyW5nLFZhiF3H3B1Wa4c1mxNsS2CI37cC0m+PyfuN65hMZXfHgMa8EtWJntZr/VxQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=microchip.com; dmarc=pass action=none header.from=microchip.com; dkim=pass header.d=microchip.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=microchiptechnology.onmicrosoft.com; s=selector2-microchiptechnology-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vGmj3Y0IIlIk6gpSt2hVgAmDTIyd+PehJrs89VgsB3E=; b=mOPeB18gsbxa6vLh4YQo9CXerowBJsk83rTS8RILYn7GUGZbfwRhakRsfmLY3bsZ2snzIoDpBRS3FFRp/6QJa97l7xf0yZiajg0aIh41rZcfHLusblAjLcqu3sDAduj55X4Oubkbxfqibbj2a+aDe9+jHSO7pwh9tygfN44JV74= Received: from CO1PR11MB4769.namprd11.prod.outlook.com (2603:10b6:303:91::21) by MN2PR11MB3616.namprd11.prod.outlook.com (2603:10b6:208:ed::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5123.31; Tue, 5 Apr 2022 15:42:42 +0000 Received: from CO1PR11MB4769.namprd11.prod.outlook.com ([fe80::6d66:3f1d:7b05:660b]) by CO1PR11MB4769.namprd11.prod.outlook.com ([fe80::6d66:3f1d:7b05:660b%6]) with mapi id 15.20.5123.031; Tue, 5 Apr 2022 15:42:42 +0000 From: To: , , , , CC: , , , Subject: Re: [PATCH 6/8] power: reset: at91-reset: add reset_controller_dev support Thread-Topic: [PATCH 6/8] power: reset: at91-reset: add reset_controller_dev support Thread-Index: AQHYSPwE63noJBr7cUyVHBDjjcHiyQ== Date: Tue, 5 Apr 2022 15:42:42 +0000 Message-ID: <923f9a0d-0a5a-99ee-a20c-db69ab44a41c@microchip.com> References: <20220405112724.2760905-1-claudiu.beznea@microchip.com> <20220405112724.2760905-7-claudiu.beznea@microchip.com> <0ff9a7cd2e6261a0de32db3bf16901e3737efef8.camel@pengutronix.de> <9683a951-160a-b4e4-9494-c2e6ee51582e@microchip.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: user-agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=microchip.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 0454216e-a798-4576-6410-08da171aec5e x-ms-traffictypediagnostic: MN2PR11MB3616:EE_ x-microsoft-antispam-prvs: x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: Cy9ODmzHla+jKp4iNPv0RqkfVH2gqD6LWWu6IYKtZQFQUGyWi6CV6ZXlLxiw6mmzY3ik0m68XYzFHqSvGykYTP2IucHQ3+YMQ/ZLw/k1PQ+TC37+XQ4plEUyzWRwCG1eMc68enrFVcfnBFXF7smY1rn0UA/rP2guJQ9dPalwso8fgomIKICkHhryJv0ImrSeVKiak7Y4mqi5PFmEaF9WuKj2E2fUC7nvOYEDIoiuN0v3NsLwqS+iO9zPfKclIPAUgpqWcYzQOSHeFSIpMCcgM9BT8fBRYqZ0oQkjsl2igc2pof2+7capq3as93+RbEWw6rxm+hx6AQnLq3qe6IPOyLdt53qpiGRUdvMVg0sMEUSDClmuuwp2E5WuSW8DK2hg9h1FtFM2g8aJR3FW69/92AczQsb0nYX3TOpOxaHKqnYfI8Sz5knzAMvfh3Xq9Xk1eWtiEF2C+eLaHaG0KC8Y/sKeo2DY311vzvujMs62pbFBh5r15+lwTsP/XtfndXhxj/szmf4D408HaIEZ3CFJ9/J+ZkwhLE1Fj6Sl8/z0Zdp5s4GYWD3QL7QM2IMBT44EIXTSW9bQfQSr3C5PVrCD3Ivt9WTNGJXqYdk4EBV4seGdX4/Fbccr4EU4sgnDzdyf75Yw8zz5N4HdhuX9Ok8myIdNLRkJmbpZil18VKyx0LMqp87w5VNCwkRmEqUPdJ6pJxfiYlerd41Mwf4jLNfVoOzLbrbw1g8m+2x6GtWqjqLJnU7Y5OvCP1TUYCLR1h2qEUUy9FhiLwyH6XzS8JM63A== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:CO1PR11MB4769.namprd11.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230001)(366004)(38100700002)(38070700005)(316002)(31686004)(6486002)(54906003)(110136005)(71200400001)(508600001)(36756003)(26005)(186003)(64756008)(66476007)(91956017)(66946007)(76116006)(66446008)(8676002)(66556008)(2906002)(8936002)(86362001)(2616005)(83380400001)(31696002)(6512007)(6506007)(53546011)(4326008)(122000001)(5660300002)(43740500002)(45980500001); DIR:OUT; SFP:1101; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?utf-8?B?QytzaGY1K1FjenVvaWFyVHVTN3pxOWlYY3lxSWR5N20vQllJZjRqc1Z2SDRW?= =?utf-8?B?ZEZHSk8rVjFNN1gyK2pWOXc4KzlRZTRXRFhtanpUOTlEWkV4Yk5zdFZ4RWR3?= =?utf-8?B?NXhSMDlZRDJPS2xhbG1QY3lrdFltWDJadmF5OEx3cHpYdG9xaDlCcWFjRjFK?= =?utf-8?B?bzdMbnU0dXNobFFzNG52ZWwrdmhENTNIVXVEODZTckpCa2E4MUxxaDRqa3NP?= =?utf-8?B?aEd2T0NxVlEyQzVKZWZkeVQ4czBBQURzejVFWXR6cHU3OEFBa2pMU1FoVStu?= =?utf-8?B?TmRlQWc0bFlkM2VwWThyQ2ZuRGN3VEkxcFBKbThjS2piYkp2NW01dno1QmZX?= =?utf-8?B?eS92c05wWnJ6Z1hvb1gzSVRVcXpsQjhLT2x5R1Vwdjg0R2N0dmM4MnJ6a25G?= =?utf-8?B?eUNsdlZNYU12REFYT0lPQUtCYTdCTnJuamhvMGJEOFF5a0pQdFZ6cEt4d2Js?= =?utf-8?B?MlVLWS94cnhjeWRiZ3g2NXlTZlZGRWV5ZVBCKzM4eVllNVcrMzFod3dhRUFv?= =?utf-8?B?MER6b1dwTjNVazUwaFFrQkEvUjA1RmJUMFJYVU9aeDIwNFZmZW1uRnhoTno5?= =?utf-8?B?d2dlUjNDbHFvWVk3VFltUUxOTUEybWlkYkhEZjN0aXpJU0ZUcnYzRHJtVFI3?= =?utf-8?B?dXJSalVKZENwTG1xQ0xNL2g3dlVBSFpRN1JhaW9pODIweUV3L1JldEMxeHFl?= =?utf-8?B?Z0c3eU4wdEEzN1hlcEV0T2N4eE4yaTdzRm5UY3pHMjlGVzJBSFZMS3d6TUsv?= =?utf-8?B?ekd3SlhOMUJzT1VSSzBHVjdYL0tVcm9tTXNvNExxdmJJSXIrNWRMVFpvblRl?= =?utf-8?B?Z2lGNVEvZTVYWjFwU0F1Q29CeElvOHozU3pjcFBmVnc5UURucUthaUpXZ0FZ?= =?utf-8?B?YzBXa3dxM2VLMVhsRXNjOURsUDBsUzVaenpJbCtuK3J4aWkzLy9oYjR0TjNN?= =?utf-8?B?ZU9acCsrN2w4K0trSGltNVFGRHM2bUFXeE9tMFVUMkJiZk5NVnZFQXl6KzBE?= =?utf-8?B?NmUvenlGZGlKeVo0M2o3b0w3Y0JzU2RyMnl0K0E5cnhkUXdHRUlMZ0Jqa0pQ?= =?utf-8?B?ZG43My93YnN0RkNURzY5dCs0b3R0MnR2TG5FcS85U0I3SWdOb1FIbU9oZFRo?= =?utf-8?B?U0lVRHI0WklRanQwaWJMcGZvdG5vODNqUE94eTRrUGlLb2xmdUhDRHhHa21Y?= =?utf-8?B?QkpMV1RmVkZlLzhycUQzbGFkQXBHYzQ0RXZoTVJkZjhUWDQ2bjJZQU41SmpQ?= =?utf-8?B?aGplM0tqUjBmS2t0VUVmUXRNbTRkS0xLOHRqOW9ENlVNcDNuUTZtVHRUWStB?= =?utf-8?B?eGx6Z25XRkU5VmRkRXRYVzU2WkRGbFNPM25FOGJvdzlHY0RZZDF5TndjcVBL?= =?utf-8?B?djJxcnpQWjJwcVBkdm1aWHBWL0FmbktvbTAyRnhwR1VUNDJlSWtIQmdxUEJN?= =?utf-8?B?Vi9jazZ3OVZtK3pZQ24zNDB6OHc4SnFQdHRCKzc0cW1hZmN3WXhCNEdCeEw3?= =?utf-8?B?WnZwSER4Q1BDNEM5N2J4UytFTVVzSHFYSGMvd0JkNXkrSkUyUm52WW9oaExK?= =?utf-8?B?NWp5NnZQckhsVXJMd2xLcUE2eVdoQkdYNk1YYkVMTFo2OVhGK1puRE1UdG5v?= =?utf-8?B?QlFaZ1FEQzE2YUt4RE5xR0ZvT3B3VzJEeGdnMFBkR1BZNzYrcnNPWEVQSTRa?= =?utf-8?B?eTVPRHhxdzRsMEQyTDhZN3V5UnIzNmhBb0FQOCtTOXNKNFNPNmY0VUZBZGtk?= =?utf-8?B?VVpxYWVucmJ0dGdmeVBnVFREWjBhWE90a1RnVU9ha0l0dmFJZW9Bd1ZxVmpH?= =?utf-8?B?dytnV1R4c3FtVEExRDdYcnhaMEFoaWhJd1A2TjMvZWh2THNJS1NyRG5MK2tJ?= =?utf-8?B?NkhqKzNyM3JrajRhbUdOT2RzRnVkL1lNTWcyTWR4TzYvN2k0L1c3N0M4RzNv?= =?utf-8?B?ZzFKWjBCL1VQT2tNTm9FeDExQ2V6OHlNVnFZRFlJYjVTcG9GUjVMMFNSVS9p?= =?utf-8?B?T1c1ZjZlTzN3N29jZzJORS9xK2hKa1pZWWhuOS9vYi9OV0NGTVE1K01VLzk2?= =?utf-8?B?UWNaSjQwclZtN3NWK0sxZm1SVS9CUWJDNVJKMHptWS94UTkreFhldWc3ajRO?= =?utf-8?B?RnFpUWZVdnlvV0NEYmhQQm1yZFhocWhQQ01vaFJkZTlUd1U5QmdCSDgreGRO?= =?utf-8?B?R1VmNkQ4R2NLcmdzQmM4K3VoSWZkcFVnckVWd0lUOE0vWVEzR29DSTlyWi9T?= =?utf-8?B?cXVUM2YzMTBsdU43bWVod2E4SjlmODFaMG9lRmE4Y0VwNEpGbXdTNEJhQUky?= =?utf-8?B?QU5vUmQ0b24xdFFLOGlkZWFhNmwrL0RoWmc3Q2JyNXN0UjA0cXAvaUZCRHFv?= =?utf-8?Q?DyixVylrHOePqJ+k=3D?= Content-ID: <643768DA49346B4C978AD610C2151C95@namprd11.prod.outlook.com> MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO1PR11MB4769.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0454216e-a798-4576-6410-08da171aec5e X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Apr 2022 15:42:42.7450 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 44MZsjTeA0RDq/faIBONHg5U6GFf0bcXtA8ub1FNAMKoH17EYIpADzWP2hCXHHwxmC4/lkU0ZQvLO5RfKwdhfafO/QDTa8TTa7uEYdoCjFU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR11MB3616 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220405_084256_925579_4BD0839F X-CRM114-Status: GOOD ( 14.82 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 05.04.2022 18:15, Philipp Zabel wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > Hi Claudio, > > On Di, 2022-04-05 at 14:47 +0000, Claudiu.Beznea@microchip.com wrote: >> Hi, Philipp, >> >> On 05.04.2022 14:47, Philipp Zabel wrote: >>> EXTERNAL EMAIL: Do not click links or open attachments unless you >>> know the content is safe >>> >>> Hi Claudiu, >>> >>> On Di, 2022-04-05 at 14:27 +0300, Claudiu Beznea wrote: >>>> SAMA7G5 reset controller has 5 extra lines that goes to different >>>> devices >>>> (3 lines to USB PHYs, 1 line to DDR controller, one line DDR PHY >>>> controller). These reset lines could be requested by different >>>> controller >>>> drivers (e.g. USB PHY driver) and these controllers' drivers >>>> could >>>> assert/deassert these lines when necessary. Thus add support for >>>> reset_controller_dev which brings this functionality. >>>> >>>> Signed-off-by: Claudiu Beznea >>>> --- >>>> drivers/power/reset/at91-reset.c | 92 >>>> ++++++++++++++++++++++++++++++-- >>>> 1 file changed, 88 insertions(+), 4 deletions(-) >>>> >>>> diff --git a/drivers/power/reset/at91-reset.c >>>> b/drivers/power/reset/at91-reset.c >>>> index 0d721e27f545..b04df54c15d2 100644 >>>> --- a/drivers/power/reset/at91-reset.c >>>> +++ b/drivers/power/reset/at91-reset.c >>>> @@ -17,6 +17,7 @@ >>>> #include >>>> #include >>>> #include >>>> +#include >>>> >>>> #include >>>> #include >>>> @@ -53,12 +54,16 @@ enum reset_type { >>>> struct at91_reset { >>>> void __iomem *rstc_base; >>>> void __iomem *ramc_base[2]; >>>> + void __iomem *dev_base; >>>> + struct reset_controller_dev rcdev; >>>> struct clk *sclk; >>>> struct notifier_block nb; >>>> u32 args; >>>> u32 ramc_lpr; >>>> }; >>>> >>>> +#define to_at91_reset(r) container_of(r, struct >>>> at91_reset, rcdev) >>>> + >>>> struct at91_reset_data { >>>> u32 reset_args; >>>> u32 n_device_reset; >>>> @@ -191,6 +196,79 @@ static const struct of_device_id >>>> at91_reset_of_match[] = { >>>> }; >>>> MODULE_DEVICE_TABLE(of, at91_reset_of_match); >>>> >>>> +static int at91_reset_update(struct reset_controller_dev *rcdev, >>>> + unsigned long id, bool assert) >>>> +{ >>>> + struct at91_reset *reset = to_at91_reset(rcdev); >>>> + u32 val; >>>> + >>>> + val = readl_relaxed(reset->dev_base); >>>> + if (assert) >>>> + val |= BIT(id); >>>> + else >>>> + val &= ~BIT(id); >>>> + writel_relaxed(val, reset->dev_base); >>> >>> This read-modify-update should be protected by a spinlock. >>> >>>> + >>>> + return 0; >>>> +} >>>> + >>>> +static int at91_reset_assert(struct reset_controller_dev *rcdev, >>>> + unsigned long id) >>>> +{ >>>> + return at91_reset_update(rcdev, id, true); >>>> +} >>>> + >>>> +static int at91_reset_deassert(struct reset_controller_dev >>>> *rcdev, >>>> + unsigned long id) >>>> +{ >>>> + return at91_reset_update(rcdev, id, false); >>>> +} >>>> + >>>> +static int at91_reset_dev_status(struct reset_controller_dev >>>> *rcdev, >>>> + unsigned long id) >>>> +{ >>>> + struct at91_reset *reset = to_at91_reset(rcdev); >>>> + u32 val; >>>> + >>>> + val = readl_relaxed(reset->dev_base); >>>> + >>>> + return !!(val & BIT(id)); >>>> +} >>>> + >>>> +static const struct reset_control_ops at91_reset_ops = { >>>> + .assert = at91_reset_assert, >>>> + .deassert = at91_reset_deassert, >>>> + .status = at91_reset_dev_status, >>>> +}; >>>> + >>>> +static int at91_reset_of_xlate(struct reset_controller_dev >>>> *rcdev, >>>> + const struct of_phandle_args >>>> *reset_spec) >>>> +{ >>>> + return reset_spec->args[0]; >>>> +} >>> >>> For 1:1 mappings there is no need for a custom of_xlate handler. >>> Just >>> leave of_xlate and of_reset_n_cells empty. >> >> I've double checked that. This would work if reset ids are continuous >> from >> zero to rcdev.nr_resets. This the of_reset_simple_xlate: >> >> static int of_reset_simple_xlate(struct reset_controller_dev *rcdev, >> const struct of_phandle_args >> *reset_spec) >> { >> if (reset_spec->args[0] >= rcdev->nr_resets) >> return -EINVAL; >> return reset_spec->args[0]; >> } >> >> But in this driver's case we have 3 ids: 4, 5, 6. That is the reason >> I had this simple xlate function. > > I see. In that case I'd say keep the custom of_xlate but let it return > -EINVAL if the args[0] value is not 4, 5, or 6. I will go for this approach (I though of it initially but let aside after) to also protect the other 2 resets (DDR controller and DDR PHY controller) which are at bits 0 and 2 in register at rstc->dev_base. Thank you, Claudiu Beznea > > Or you could set nr_resets to 7, but unless there are more resets at > the lower bits, that wouldn't necessarily be better. > > regards > Philipp _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel