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Fri, 11 Oct 2024 12:01:38 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id D904C40054; Fri, 11 Oct 2024 12:00:05 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 6566E268186; Fri, 11 Oct 2024 11:57:06 +0200 (CEST) Received: from [10.252.28.117] (10.252.28.117) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Fri, 11 Oct 2024 11:57:05 +0200 Message-ID: <9283caeb-1b84-43c2-a8a4-6b43a6962f34@foss.st.com> Date: Fri, 11 Oct 2024 11:55:59 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/4] hwrng: stm32 - implement support for STM32MP25x platforms To: Marek Vasut , Olivia Mackall , Herbert Xu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: =?UTF-8?Q?Uwe_Kleine-K=C3=B6nig?= , Lionel Debieve , , , , , , Yang Yingliang References: <20241007132721.168428-1-gatien.chevallier@foss.st.com> <20241007132721.168428-3-gatien.chevallier@foss.st.com> <2fad1566-49f9-4586-b0d4-8a4a12f9e69e@denx.de> Content-Language: en-US From: Gatien CHEVALLIER In-Reply-To: <2fad1566-49f9-4586-b0d4-8a4a12f9e69e@denx.de> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.252.28.117] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241011_030200_306560_50C920E1 X-CRM114-Status: GOOD ( 11.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10/7/24 15:54, Marek Vasut wrote: > On 10/7/24 3:27 PM, Gatien Chevallier wrote: >> Implement the support for STM32MP25x platforms. On this platform, a >> security clock is shared between some hardware blocks. For the RNG, >> it is the RNG kernel clock. Therefore, the gate is no more shared >> between the RNG bus and kernel clocks as on STM32MP1x platforms and >> the bus clock has to be managed on its own. >> >> Signed-off-by: Gatien Chevallier > A bit of a higher-level design question -- can you use > drivers/clk/clk-bulk.c clk_bulk_*() to handle all these disparate count > of clock easily ? Hi, I'd like to make sure that we enable the core clock before the bus clock so that the RNG hardware block can start its internal tests while we ungate the bus clock. It's not a strong opinion but it feels better. Cheers, Gatien