From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ADD7FC83F2C for ; Tue, 5 Sep 2023 11:18:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Q7sC8Vc0mNfDRYPtfZjn/ELNdgv2k9X5biXRHd/U5EM=; b=PuTYFcjuAPSZwe 1D3An2HaF8XVaaqTGi4+mUERN27TPeE1VD17iKaK6o4sHxtcJUaJhprY523zIwunFJe6XQsJdndnL ixJiE02aGIdnM9sRYmoHnU4rTrdREAGCvlCoEpdQeKynLjUV2iuk2q70ujckAtIjPQeRcCmJhhRyC QApP4350H1ZHSogCZoJnJO+LytP8YU0jDeDZJ/TpDGbrlW7sHNX3q1D5Cc2k8muA0ft8iHlJ+u23l QIhZ5VMgTWWQ6aMQUtBV5qSPFAVUp/pULBYGE3y7sc1oF/G33vLCix/9jIQ/N0tSpiKr4fkGW7ogK K4k0Uiwm/3rb/Z2wW8SA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qdU4Q-005tR8-38; Tue, 05 Sep 2023 11:18:10 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1qdU4N-005tQY-1t for linux-arm-kernel@lists.infradead.org; Tue, 05 Sep 2023 11:18:09 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 31E9611FB; Tue, 5 Sep 2023 04:18:39 -0700 (PDT) Received: from [10.1.196.40] (e121345-lin.cambridge.arm.com [10.1.196.40]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CF5BA3F64C; Tue, 5 Sep 2023 04:17:59 -0700 (PDT) Message-ID: <932355b4-7d43-a465-a2da-8dded8e2d069@arm.com> Date: Tue, 5 Sep 2023 12:17:51 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux aarch64; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH 1/2] dt-bindings: interrupt-controller: arm,gic-v3: Add dma-noncoherent property Content-Language: en-GB To: Lorenzo Pieralisi , linux-kernel@vger.kernel.org Cc: Rob Herring , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Mark Rutland , Rob Herring , Fang Xiang , Marc Zyngier References: <20230905104721.52199-1-lpieralisi@kernel.org> <20230905104721.52199-2-lpieralisi@kernel.org> From: Robin Murphy In-Reply-To: <20230905104721.52199-2-lpieralisi@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230905_041807_675586_C4CB3750 X-CRM114-Status: GOOD ( 19.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 05/09/2023 11:47 am, Lorenzo Pieralisi wrote: > The GIC v3 specifications allow redistributors and ITSes interconnect > ports used to access memory to be wired up in a way that makes the > respective initiators/memory observers non-coherent. > > Add the standard dma-noncoherent property to the GICv3 bindings to > allow firmware to describe the redistributors/ITSes components and > interconnect ports behaviour in system designs where the redistributors > and ITSes are not coherent with the CPU. > > Signed-off-by: Lorenzo Pieralisi > Cc: Rob Herring > --- > .../bindings/interrupt-controller/arm,gic-v3.yaml | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml > index 39e64c7f6360..0a81ae4519a6 100644 > --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml > +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml > @@ -106,6 +106,10 @@ properties: > $ref: /schemas/types.yaml#/definitions/uint32 > maximum: 4096 > > + dma-noncoherent: > + description: | > + Present if the GIC redistributors are not cache coherent with the CPU. I wonder if it's worth being a bit more specific here, e.g. "if the GIC {redistributors,ITS} permit programming cacheable inner-shareable memory attributes, but are connected to a non-coherent downstream interconnect." That might help clarify why the negative property, which could seem a bit backwards at first glance, and that it's not so important in the cases where the GIC itself is fundamentally non-coherent anyway (which *is* software-discoverable). Otherwise, this is the same approach that I like and have previously lobbied for, so obviously I approve :) (plus I do think it's the right shape to be able to slot an equivalent field into ACPI MADT entries without *too* much bother) Thanks, Robin. > + > msi-controller: > description: > Only present if the Message Based Interrupt functionality is > @@ -193,6 +197,10 @@ patternProperties: > compatible: > const: arm,gic-v3-its > > + dma-noncoherent: > + description: | > + Present if the GIC ITS is not cache coherent with the CPU. > + > msi-controller: true > > "#msi-cells": _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel