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Thu, 05 Dec 2024 12:50:57 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 907B640044; Thu, 5 Dec 2024 12:49:26 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 454DE29BB01; Thu, 5 Dec 2024 12:46:38 +0100 (CET) Received: from [10.129.178.212] (10.129.178.212) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.37; Thu, 5 Dec 2024 12:46:37 +0100 Message-ID: <9340979e-8f0e-465b-a524-4ff315a9941d@foss.st.com> Date: Thu, 5 Dec 2024 12:46:29 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Christian Bruel Subject: Re: [PATCH v2 2/5] PCI: stm32: Add PCIe host support for STM32MP25 To: Lucas Stach , Bjorn Helgaas , Rob Herring CC: , , , , , , , , , , , , , , , , , References: <20241129205822.GA2772018@bhelgaas> <9ca967aea19d6c28327f3a9bb77e23f6245603e9.camel@pengutronix.de> Content-Language: en-US In-Reply-To: <9ca967aea19d6c28327f3a9bb77e23f6245603e9.camel@pengutronix.de> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.129.178.212] X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241205_035121_089006_0D5B49B8 X-CRM114-Status: GOOD ( 17.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hello Bjorn and Lucas, On 11/29/24 22:18, Lucas Stach wrote: > Am Freitag, dem 29.11.2024 um 14:58 -0600 schrieb Bjorn Helgaas: >> [+to Rob, DMA mask question] >> >> On Tue, Nov 26, 2024 at 04:51:16PM +0100, Christian Bruel wrote: >>> Add driver for the STM32MP25 SoC PCIe Gen2 controller based on the >>> DesignWare PCIe core. >> >> Can you include the numeric rate, not just "gen2", so we don't have to >> search for it? >> >>> +static int stm32_pcie_resume_noirq(struct device *dev) >>> +{ >>> + struct stm32_pcie *stm32_pcie = dev_get_drvdata(dev); >>> + struct dw_pcie *pci = stm32_pcie->pci; >>> + struct dw_pcie_rp *pp = &pci->pp; >>> + int ret; >>> + >>> + /* init_state must be called first to force clk_req# gpio when no >>> + * device is plugged. >>> + */ >> >> Use drivers/pci/ conventional comment style: >> >> /* >> * text ... >> */ >> >>> +static bool is_stm32_pcie_driver(struct device *dev) >>> +{ >>> + /* PCI bridge */ >>> + dev = get_device(dev); >>> + >>> + /* Platform driver */ >>> + dev = get_device(dev->parent); >>> + >>> + return (dev->driver == &stm32_pcie_driver.driver); >>> +} >>> + >>> +/* >>> + * DMA masters can only access the first 4GB of memory space, >>> + * so we setup the bus DMA limit accordingly. >>> + */ >>> +static int stm32_dma_limit(struct pci_dev *pdev, void *data) >>> +{ >>> + dev_dbg(&pdev->dev, "disabling DMA DAC for device"); >>> + >>> + pdev->dev.bus_dma_limit = DMA_BIT_MASK(32); >> >> I don't think this is the right way to do this. Surely there's a way >> to describe the DMA capability of the bridge once instead of iterating >> over all the downstream devices? This quirk can't work for hot-added >> devices anyway. >> agree, > This should simply be a dma-ranges property in the PCIe host controller > DT node, which should describe the DMA address range limits for > transactions passing through the host. far better indeed, dma-ranges works like a charm thanks, > > Regards, > Lucas > >>> + return 0; >>> +} >>> + >>> +static void quirk_stm32_dma_mask(struct pci_dev *pci) >>> +{ >>> + struct pci_dev *root_port; >>> + >>> + root_port = pcie_find_root_port(pci); >>> + >>> + if (root_port && is_stm32_pcie_driver(root_port->dev.parent)) >>> + pci_walk_bus(pci->bus, stm32_dma_limit, NULL); >>> +} >>> +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SYNOPSYS, 0x0550, quirk_stm32_dma_mask); >> >