From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A3382CD11C2 for ; Fri, 5 Apr 2024 14:11:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:Cc:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=PdfLu2QLdYLfKM+0v/uvwnHQYORjfCP++rLNKOb9kTE=; b=S0BLdQsFHS1ijg vORB8y5J7QDth3x83OHJth9ED03u1lQwsvN07KKiWbqC6oKDCJXCwqCkKSAgjq3oogzoTZ25IYBO7 Ge3Kasw48oTL1Bo3Tejpqgi8fE+U/SdBG6utLmPqY8+LCF5Ea1P5Hdv1Vlcc9oJK2Ui6GqApx8BSk SXNNf23PTQet8+LTM/NO8A165vxCuCID+hsO8g0vk1ibR3qbu05Kc8eKmbVGlgSg91oaACCihd3R3 ozI1l4yvj502eyCGABhvdFLdSNR7oTZis38UeB8Y3W6yUvJJOn6KOuUVX0ilOsIcm9R5i33u/Xzup 63kPE/lVdUhsWACeopSg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rskHL-00000007Nnb-1MAa; Fri, 05 Apr 2024 14:10:51 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.97.1 #2 (Red Hat Linux)) id 1rskHI-00000007NlT-0qsi for linux-arm-kernel@lists.infradead.org; Fri, 05 Apr 2024 14:10:49 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B7941FEC; Fri, 5 Apr 2024 07:11:17 -0700 (PDT) Received: from [10.57.54.111] (unknown [10.57.54.111]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 222D73F7B4; Fri, 5 Apr 2024 07:10:44 -0700 (PDT) Message-ID: <94af4af9-8cef-4673-bce5-16bd5edb28dd@arm.com> Date: Fri, 5 Apr 2024 15:10:41 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] arm64: Fix double TCR_T0SZ_OFFSET shift Content-Language: en-GB To: Seongsu Park , catalin.marinas@arm.com, will@kernel.org, ardb@kernel.org, mark.rutland@arm.com Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Leem ChaeHoon , Gyeonggeon Choi , Soomin Cho , DaeRo Lee , kmasta References: <20240402104735.170539-1-sgsu.park@samsung.com> From: Robin Murphy In-Reply-To: <20240402104735.170539-1-sgsu.park@samsung.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240405_071048_557998_04A1A602 X-CRM114-Status: GOOD ( 13.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2024-04-02 11:47 am, Seongsu Park wrote: > We have already shifted the value of t0sz in TCR_T0SZ by TCR_T0SZ_OFFSET. > So, the TCR_T0SZ_OFFSET shift here should be removed. If the shift for assigning the t0sz value to the TCR field is wrong, then the other shift for comparing the same t0sz value to the existing TCR field must also be wrong. Really, this many people involved in writing a patch and still nobody spotted the obvious? Thanks, Robin. > Co-developed-by: Leem ChaeHoon > Signed-off-by: Leem ChaeHoon > Co-developed-by: Gyeonggeon Choi > Signed-off-by: Gyeonggeon Choi > Co-developed-by: Soomin Cho > Signed-off-by: Soomin Cho > Co-developed-by: DaeRo Lee > Signed-off-by: DaeRo Lee > Co-developed-by: kmasta > Signed-off-by: kmasta > Signed-off-by: Seongsu Park > --- > arch/arm64/include/asm/mmu_context.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h > index c768d16b81a4..58de99836d2e 100644 > --- a/arch/arm64/include/asm/mmu_context.h > +++ b/arch/arm64/include/asm/mmu_context.h > @@ -76,7 +76,7 @@ static inline void __cpu_set_tcr_t0sz(unsigned long t0sz) > return; > > tcr &= ~TCR_T0SZ_MASK; > - tcr |= t0sz << TCR_T0SZ_OFFSET; > + tcr |= t0sz; > write_sysreg(tcr, tcr_el1); > isb(); > } _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel