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Mon, 28 Oct 2024 11:51:37 -0700 (PDT) Received: from [10.28.17.173] ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6d179a068d1sm34605066d6.101.2024.10.28.11.51.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 28 Oct 2024 11:51:36 -0700 (PDT) Message-ID: <954d6c11-ab4e-485f-8152-94bf38625f9c@broadcom.com> Date: Mon, 28 Oct 2024 14:51:34 -0400 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Beta Subject: Re: [PATCH 1/1] RFC: dt bindings: Add property "brcm,gen3-eq-presets" To: Krishna Chaitanya Chundru , Rob Herring Cc: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, Florian Fainelli , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley , "moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE" , "moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , open list References: <20241018182247.41130-1-james.quinlan@broadcom.com> <20241018182247.41130-2-james.quinlan@broadcom.com> <20241021190334.GA953710-robh@kernel.org> <77d3a1a9-c22d-0fd3-5942-91b9a3d74a43@quicinc.com> Content-Language: en-US From: James Quinlan Autocrypt: addr=james.quinlan@broadcom.com; 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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241028_115140_380455_A6A90B9D X-CRM114-Status: GOOD ( 23.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10/24/24 21:08, Krishna Chaitanya Chundru wrote: > > > On 10/22/2024 12:33 AM, Rob Herring wrote: >> On Fri, Oct 18, 2024 at 02:22:45PM -0400, Jim Quinlan wrote: >>> Support configuration of the GEN3 preset equalization settings, aka the >>> Lane Equalization Control Register(s) of the Secondary PCI Express >>> Extended Capability.  These registers are of type HwInit/RsvdP and >>> typically set by FW.  In our case they are set by our RC host bridge >>> driver using internal registers. >>> >>> Signed-off-by: Jim Quinlan >>> --- >>>   .../devicetree/bindings/pci/brcm,stb-pcie.yaml       | 12 >>> ++++++++++++ >>>   1 file changed, 12 insertions(+) >>> >>> diff --git >>> a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml >>> b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml >>> index 0925c520195a..f965ad57f32f 100644 >>> --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml >>> +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml >>> @@ -104,6 +104,18 @@ properties: >>>       minItems: 1 >>>       maxItems: 3 >>>   +  brcm,gen3-eq-presets: >>> +    description: | >>> +      A u16 array giving the GEN3 equilization presets, one for >>> each lane. >>> +      These values are destined for the 16bit registers known as the >>> +      Lane Equalization Control Register(s) of the Secondary PCI >>> Express >>> +      Extended Capability.  In the array, lane 0 is first term, >>> lane 1 next, >>> +      etc. The contents of the entries reflect what is necessary for >>> +      the current board and SoC, and the details of each preset are >>> +      described in Section 7.27.4 of the PCI base spec, Revision 3.0. >> >> If these are defined by the PCIe spec, then why is it Broadcom specific >> property? Yes, I will remove the "brcm," prefix. >> > Hi Rob, > > qcom pcie driver also needs to program these presets as you suggested > this can go to common pci bridge binding. > > from PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4.2 for data rates > of  8.0 GT/s, 16.0 GT/s, and 32.0 GT/s uses one class of preset (P0 > through P10) and where as data rates of 64.0 GT/s use different class of > presets (Q0 through Q10) (Table 4-23). And data rates of 8.0 GT/s also > have optional preset hints (Table 4-24). > > And there is possibility that for each data rate we may require > different preset configuration. > > Can we have a dt binding for each data rate of 16 byte array. > like gen3-eq-preset array, gen4-eq-preset array etc. Yes, that was the idea when using "genX-eq-preset", for X in {3,4...}. Keep in mind that this is an RFC; I have a backlog of commit submissions before I can submit the code that uses this DT property.  If you (Krishna) want to submit something now I'd be quite happy to go with that.  I don't believe it is acceptable to submit a bindings commit w/o code that uses it (if I'm incorrect I'll be glad to do a V2). Regards, Jim Quinlan Broadcom STB/CM > > - Krishna Chaitanya >>> + >>> +    $ref: /schemas/types.yaml#/definitions/uint16-array >> >> minItems: 1 >> maxItems: 16 >> >> Last I saw, you can only have up to 16 lanes. >> >> Rob >>