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Mon, 22 Apr 2024 15:26:21 -0700 (PDT) Received: from [10.67.48.245] ([192.19.223.252]) by smtp.googlemail.com with ESMTPSA id k63-20020a638442000000b005fd88b393b4sm3381015pgd.59.2024.04.22.15.26.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 22 Apr 2024 15:26:20 -0700 (PDT) Message-ID: <958c27b1-26d7-4927-976b-4502f33f31f7@gmail.com> Date: Mon, 22 Apr 2024 15:26:16 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] irqchip/irq-brcmstb-l2: Avoid saving mask on shutdown To: Thomas Gleixner , Florian Fainelli , linux-kernel@vger.kernel.org Cc: opendmb@gmail.com, Tim Ross , Broadcom internal kernel review list , "open list:BROADCOM BMIPS MIPS ARCHITECTURE" , "moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE" References: <20240416194343.469318-1-florian.fainelli@broadcom.com> <87le55ulw5.ffs@tglx> Content-Language: en-US From: Florian Fainelli In-Reply-To: <87le55ulw5.ffs@tglx> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240422_152626_192297_4CCF04D8 X-CRM114-Status: GOOD ( 17.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 4/22/24 14:29, Thomas Gleixner wrote: > On Tue, Apr 16 2024 at 12:43, Florian Fainelli wrote: >> The interrupt controller shutdown path does not need to save the mask of >> enabled interrupts because the next state the system is going to be in >> is akin to a cold boot, or a kexec'd kernel. > > Sure, but > >> Reported-by: Tim Ross >> Signed-off-by: Florian Fainelli >> --- >> drivers/irqchip/irq-brcmstb-l2.c | 17 ++++++++++++++--- >> 1 file changed, 14 insertions(+), 3 deletions(-) >> >> diff --git a/drivers/irqchip/irq-brcmstb-l2.c b/drivers/irqchip/irq-brcmstb-l2.c >> index 2b0b3175cea0..c988886917f7 100644 >> --- a/drivers/irqchip/irq-brcmstb-l2.c >> +++ b/drivers/irqchip/irq-brcmstb-l2.c >> @@ -118,7 +118,7 @@ static void brcmstb_l2_intc_irq_handle(struct irq_desc *desc) >> chained_irq_exit(chip, desc); >> } >> >> -static void brcmstb_l2_intc_suspend(struct irq_data *d) >> +static void __brcmstb_l2_intc_suspend(struct irq_data *d, bool save) >> { >> struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); >> struct irq_chip_type *ct = irq_data_get_chip_type(d); >> @@ -127,7 +127,8 @@ static void brcmstb_l2_intc_suspend(struct irq_data *d) >> >> irq_gc_lock_irqsave(gc, flags); >> /* Save the current mask */ >> - b->saved_mask = irq_reg_readl(gc, ct->regs.mask); >> + if (save) >> + b->saved_mask = irq_reg_readl(gc, ct->regs.mask); > > what's the conditional actually buying you except more complex code? Not much this is an optimization that is simple to carry out. There can be dozens of such L2 interrupt controllers in a given system and the MMIO accesses start adding up eventually. -- Florian _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel