From: Marc Zyngier <maz@kernel.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: mark.rutland@arm.com, saiprakash.ranjan@codeaurora.org,
kernel-team@android.com, anshuman.khandual@arm.com,
catalin.marinas@arm.com, linux-kernel@vger.kernel.org,
dianders@chromium.org, will@kernel.org,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 8/8] arm64: cpufeature: Add an overview comment for the cpufeature framework
Date: Thu, 16 Apr 2020 16:26:05 +0100 [thread overview]
Message-ID: <96438d59a2bc05871ef68fca475fabf5@kernel.org> (raw)
In-Reply-To: <96dd797d-ccfe-c867-0a70-65eccacde3cd@arm.com>
On 2020-04-16 15:59, Suzuki K Poulose wrote:
Hi Suzuki,
[...]
> As you mentioned in the other response we could add information about
> the guest view, something like :
>
> - KVM exposes the sanitised value of the feature registers to the
> guests and is not affected by the FTR_VISIBLE. However,
> depending on the individual feature support in the hypervisor,
> some of the fields may be capped/limited.
Although in most cases, what KVM exposes is indeed a strict subset of
the host's features, there is a few corner cases where we expose
features
that do not necessarily exist on the host. For example ARMv8.5-GTG and
ARMv8.4-TTL get exposed by the NV patches even if they don't exist on
the
host, as KVM will actually emulate them.
Not a big deal, but I just wanted to outline that it isn't as clear-cut
as
it may seem...
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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next prev parent reply other threads:[~2020-04-16 15:28 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-14 21:31 [PATCH 0/8] Relax sanity checking for mismatched AArch32 EL1 Will Deacon
2020-04-14 21:31 ` [PATCH 1/8] arm64: cpufeature: Relax check for IESB support Will Deacon
2020-04-15 10:02 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 2/8] arm64: cpufeature: Spell out register fields for ID_ISAR4 and ID_PFR1 Will Deacon
2020-04-15 10:09 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 3/8] arm64: cpufeature: Add CPU capability for AArch32 EL1 support Will Deacon
2020-04-15 8:55 ` Marc Zyngier
2020-04-15 17:00 ` Will Deacon
2020-04-15 10:13 ` Suzuki K Poulose
2020-04-15 10:14 ` Will Deacon
2020-04-15 13:15 ` Suzuki K Poulose
2020-04-15 13:22 ` Marc Zyngier
2020-04-17 9:44 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 4/8] arm64: cpufeature: Remove redundant call to id_aa64pfr0_32bit_el0() Will Deacon
2020-04-15 10:25 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 5/8] arm64: cpufeature: Factor out checking of AArch32 features Will Deacon
2020-04-15 10:36 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 6/8] arm64: cpufeature: Relax AArch32 system checks if EL1 is 64-bit only Will Deacon
2020-04-15 10:43 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 7/8] arm64: cpufeature: Relax checks for AArch32 support at EL[0-2] Will Deacon
2020-04-15 10:50 ` Suzuki K Poulose
2020-04-15 10:58 ` Will Deacon
2020-04-15 11:37 ` Suzuki K Poulose
2020-04-15 12:29 ` Will Deacon
2020-04-17 9:37 ` Suzuki K Poulose
2020-04-14 21:31 ` [PATCH 8/8] arm64: cpufeature: Add an overview comment for the cpufeature framework Will Deacon
2020-04-16 11:58 ` Will Deacon
2020-04-16 14:59 ` Suzuki K Poulose
2020-04-16 15:26 ` Marc Zyngier [this message]
2020-04-16 18:12 ` Will Deacon
2020-04-16 8:39 ` [PATCH 0/8] Relax sanity checking for mismatched AArch32 EL1 Sai Prakash Ranjan
2020-04-16 10:26 ` Sai Prakash Ranjan
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