Re: [PATCH v7 06/10] drm: bridge: samsung-dsim: Add platform PLL_P (PMS_P) offset

Marek Vasut
2022-10-15T21:57:24Z

On 10/5/22 17:13, Jagan Teki wrote:
> Look like PLL PMS_P offset value varies between platforms that have
> Samsung DSIM IP.
>
> However, there is no clear evidence for it as both Exynos and i.MX
> 8M Mini Application Processor Reference Manual is still referring
> the PMS_P offset as 13.
>
> The offset 13 is not working for i.MX8M Mini SoCs but the downstream
> NXP sec-dsim.c driver is using offset 14 for i.MX8M Mini SoC platforms
> [1] [2].
>
> PMS_P value set in sec_mipi_dsim_check_pll_out using PLLCTRL_SET_P()
> with offset 13 and then an additional offset of one bit added in
> sec_mipi_dsim_config_pll via PLLCTRL_SET_PMS().
>
> Not sure whether it is reference manual documentation or something else
> but this patch trusts the downstream code and handle PLL_P offset via
> platform driver data so-that imx8mm driver data shall use pll_p_offset
> to 14.
>
> [1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n210
> [2] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n211

You also add to the commit message that all of 8M Mini/Nano/Plus have
P=14 , unlike Exynos. It also seems like the PLL in the DSIM and the
clock PLLs in the 8M are the same design from Samsung.

Reviewed-by: Marek Vasut <marex@denx.de>