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Thu, 04 Dec 2025 02:55:39 -0800 (PST) Received: from [192.168.1.3] ([185.48.77.170]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-42f7cbff320sm2520602f8f.18.2025.12.04.02.55.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 04 Dec 2025 02:55:38 -0800 (PST) Message-ID: <96c54895-cebe-4247-86e6-d41b8be0dd40@linaro.org> Date: Thu, 4 Dec 2025 10:55:37 +0000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/7] perf cs-etm: Don't use hard coded config bits when setting up ETMCR From: James Clark To: Leo Yan Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , Suzuki K Poulose , Mike Leach , John Garry , Will Deacon , Leo Yan , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org References: <20251201-james-perf-config-bits-v1-0-22ecbbf8007c@linaro.org> <20251201-james-perf-config-bits-v1-4-22ecbbf8007c@linaro.org> <20251202114300.GV724103@e132581.arm.com> <53b24702-eb3b-4e08-bca3-70402eaf4db5@linaro.org> Content-Language: en-US In-Reply-To: <53b24702-eb3b-4e08-bca3-70402eaf4db5@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251204_025541_413675_F16FFE22 X-CRM114-Status: GOOD ( 19.80 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 02/12/2025 11:53 am, James Clark wrote: > > > On 02/12/2025 11:43 am, Leo Yan wrote: >> On Mon, Dec 01, 2025 at 04:41:07PM +0000, Coresight ML wrote: >> >> [...] >> >>> @@ -746,7 +779,7 @@ static void cs_etm_get_metadata(struct perf_cpu >>> cpu, u32 *offset, >>>       case CS_ETMV3: >>>           magic = __perf_cs_etmv3_magic; >>>           /* Get configuration register */ >>> -        info->priv[*offset + CS_ETM_ETMCR] = cs_etm_get_config(itr); >>> +        info->priv[*offset + CS_ETM_ETMCR] = cs_etm_guess_etmcr(itr); >> >> I still think cs_etm_get_config() is better than cs_etm_guess_etmcr(). >> >> For ETMv3, we directly pass CONFIG to the kernel, and after validation >> in the dirver, then the value will be set to ETMCR.  If we already know >> the config value is consistent between user space and kernel, why One other note is that since moving the timestamp field, this is no longer true either. The value in attr.config isn't directly put into ETMCR. >> introduce a redundant "guess" operation here? >> >> Thanks, >> Leo > > Because userspace doesn't always come up with the same value as the > driver. For example right now in ETM3, ETMCR_RETURN_STACK isn't set > depending on certain conditions that userspace doesn't know about.  ETM4 > has the same for TRCCONFIGR_RS and maybe some others. In the future, > other versions of the driver could do different things as long as we > don't break decoding. > > I didn't want the function name to imply it was doing something it > wasn't as that confused me a little bit. It's definitely not "getting" > the value. Maybe "guess" isn't the best it could be, but it's not far off. >