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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a78e497230sm8991834a91.11.2026.10.04.20.08.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 04 Oct 2026 20:08:05 -0700 (PDT) Message-ID: <9706e01c-9c90-4dbc-a694-7f88bf7ee38c@gmail.com> Date: Mon, 5 Oct 2026 11:08:02 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] spi: dt-bindings: nuvoton,ma35d1-qspi: Add MA35D1 SPI controller To: Krzysztof Kozlowski Cc: broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cwweng@nuvoton.com References: <20261001131818.110028-1-cwweng.linux@gmail.com> <20261001131818.110028-2-cwweng.linux@gmail.com> <20261003-innocent-placid-markhor-e7c6ec@quoll> Content-Language: en-US From: Chi-Wen Weng In-Reply-To: <20261003-innocent-placid-markhor-e7c6ec@quoll> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261004_200808_610176_0088BD6B X-CRM114-Status: GOOD ( 22.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Krzysztof Kozlowski 於 2026/10/3 下午 10:25 寫道: > On Thu, Oct 01, 2026 at 09:18:16PM +0800, Chi-Wen Weng wrote: >> From: Chi-Wen Weng >> >> Extend the existing MA35D1 QSPI binding to also describe the MA35D1 SPI >> controller. >> >> The SPI and QSPI controllers are separate hardware IPs. QSPI additionally >> supports dual, quad and DTR transfers and a target-mode timeout function, >> but these differences do not require additional controller-specific >> Devicetree properties. >> >> Both controllers expose the same Devicetree-visible resources and provide >> up to two native chip-select signals. GPIO chip selects are supported >> through the generic SPI controller binding. Since the MA35D1 QSPI driver >> now supports GPIO chip selects, also remove the existing restriction >> on cs-gpios for the QSPI compatible. > > This has to be a separate commit. > >> >> Add the nuvoton,ma35d1-spi compatible and update the binding description >> and examples to cover both controllers. >> >> Signed-off-by: Chi-Wen Weng >> --- >> .../bindings/spi/nuvoton,ma35d1-qspi.yaml | 41 +++++++++++++++++-- >> 1 file changed, 37 insertions(+), 4 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml >> index 40965ec5163b..72f2e1e1219a 100644 >> --- a/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml >> +++ b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml >> @@ -4,7 +4,17 @@ >> $id: http://devicetree.org/schemas/spi/nuvoton,ma35d1-qspi.yaml# >> $schema: http://devicetree.org/meta-schemas/core.yaml# >> >> -title: Nuvoton MA35D1 Quad SPI Controller >> +title: Nuvoton MA35D1 SPI and Quad SPI Controllers >> + >> +description: | >> + The Nuvoton MA35D1 SoC contains separate SPI and QSPI controller IPs. >> + Both controllers expose the same Devicetree-visible resources and provide >> + two native chip-select signals. GPIO chip selects are supported through the >> + generic SPI controller binding. >> + >> + The QSPI controller additionally supports dual, quad and DTR transfers and >> + a target-mode timeout function. These capability differences do not require >> + additional controller properties. >> >> maintainers: >> - Chi-Wen Weng >> @@ -14,7 +24,9 @@ allOf: >> >> properties: >> compatible: >> - const: nuvoton,ma35d1-qspi >> + enum: >> + - nuvoton,ma35d1-spi >> + - nuvoton,ma35d1-qspi >> >> reg: >> maxItems: 1 >> @@ -33,8 +45,6 @@ properties: >> maximum: 2 >> default: 2 >> >> - cs-gpios: false >> - >> required: >> - compatible >> - reg >> @@ -59,7 +69,30 @@ examples: >> interrupts = ; >> clocks = <&clk QSPI0_GATE>; >> resets = <&sys MA35D1_RESET_QSPI0>; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + }; >> + >> + - | >> + #include >> + #include >> + #include >> + > > No need for a new example, for exactly the same node. Difference in > value of a property does not justify it. > > Best regards, > Krzysztof Hi Krzysztof, Thanks for the review. I will address both comments in v3. For the binding changes, I will split the current patch into two separate commits: 1. Extend the existing MA35D1 QSPI binding to also describe the MA35D1 SPI controller. This patch will only update the title, description and compatible list to cover both the SPI and QSPI controllers. The existing `cs-gpios: false` restriction will remain in this commit. 2. Add a separate binding patch to allow GPIO chip selects. This patch will remove the existing `cs-gpios: false` restriction so that the generic SPI controller binding can provide GPIO chip-select support. I will also drop the additional SPI example. Since the SPI and QSPI controllers use the same node structure and only differ in property values, the existing example is sufficient. So the v3 series is planned as: 1. spi: dt-bindings: nuvoton,ma35d1-qspi: Add MA35D1 SPI controller 2. spi: dt-bindings: nuvoton,ma35d1-qspi: Allow GPIO chip selects 3. spi: ma35d1: Add Nuvoton MA35D1 SPI controller support 4. spi: ma35d1-qspi: Add GPIO chip select support Thanks, Chi-Wen