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Wed, 15 Apr 2026 03:23:05 +0000 (GMT) Received: from nasanex01a.na.qualcomm.com (nasanex01a.na.qualcomm.com [10.52.223.231]) by NASANPPMTA01.qualcomm.com (8.18.1.7/8.18.1.7) with ESMTPS id 63F3N42r025390 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Apr 2026 03:23:04 GMT Received: from [10.233.71.148] (10.80.80.8) by nasanex01a.na.qualcomm.com (10.52.223.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Tue, 14 Apr 2026 20:23:01 -0700 Message-ID: <9772e300-06cb-4892-810c-bdcf6251bf9f@quicinc.com> Date: Wed, 15 Apr 2026 11:22:49 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 0/4] Add Qualcomm extended CTI support To: Yingchao Deng , Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin CC: , , , , Jinlong Mao , Tingwei Zhang , Jie Gan , Yingchao Deng References: <20260325-extended_cti-v7-0-bb406005089f@oss.qualcomm.com> Content-Language: en-US From: "Yingchao Deng (Consultant)" In-Reply-To: <20260325-extended_cti-v7-0-bb406005089f@oss.qualcomm.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01a.na.qualcomm.com (10.52.223.231) X-QCInternal: smtphost X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDE1MDAyOCBTYWx0ZWRfX1VaQpHqArrD7 E5I+Hr5U4H8MzItwYAi2/ybTLXzzOp/hJCVhZEjSGMLiEPOAXYEMY+rAwAcKCxWtsp5f8F5dg0H TS/iHePhASnPb//EN76Dl+lI4HqzPmrffximkoU2WxAdNg0O7ATjffQ+dZUkoAcjvYp+Lotdpq/ X5hl1o5SgbOBMHnj3cIJ0Ixftj8pxR+lfBgQLkMzVMJ6+sUrcJBqcC2C4LE314LWfFlW8eKXms1 qBW0npkVL73/t6lih32qNutu5qRb0VSX+9qihRloqPs4Uq5m00Yb03yGfOwG4+SWvWJiFxbeuwF EfVZ5ufqWEPGZoDmNFnx6bOQamkOTnsWfHrUw3+sNKFPI0aKWYC9MnuMqal8HABMzpyluZSzwH1 ZoTzyCflup0YrzA4fkCxt/0ieS0HbtjM1nCO5gj/lfXNbZ5mNi2a5jFrREGDBuyy2tNL04zjk/m bfeVqTkN/Yg2sE/0Aeg== X-Proofpoint-ORIG-GUID: G6ntLghWieHUcqT-liZgDVIM6TJp7O5c X-Proofpoint-GUID: G6ntLghWieHUcqT-liZgDVIM6TJp7O5c X-Authority-Analysis: v=2.4 cv=afFRWxot c=1 sm=1 tr=0 ts=69df0499 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=BrGTpx9XV5RcIlctfScA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-14_04,2026-04-13_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 impostorscore=0 clxscore=1011 lowpriorityscore=0 priorityscore=1501 bulkscore=0 suspectscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604150028 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260414_202312_363733_90F1352C X-CRM114-Status: GOOD ( 23.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 3/25/2026 1:43 PM, Yingchao Deng wrote: > The Qualcomm extended CTI is a heavily parameterized version of ARM’s > CSCTI. It allows a debugger to send to trigger events to a processor or to > send a trigger event to one or more processors when a trigger event occurs > on another processor on the same SoC, or even between SoCs. > > Qualcomm extended CTI supports up to 128 triggers. And some of the register > offsets are changed. > > The commands to configure CTI triggers are the same as ARM's CTI. > > Prerequisites: > This series depends on the following CoreSight fix: > [PATCH v2 1/1] coresight: fix issue where coresight component has no claimtags > Link: https://lore.kernel.org/all/20251027223545.2801-2-mike.leach@linaro.org/ > > Changes in v7: > 1. Split the extended CTI support into smaller, logically independent > patches to improve reviewability. > 2. Removed the dual offset-array based register access used in v6 for > standard and Qualcomm CTIs. Register addressing is now unified through > a single code path by encoding the register index together with the base > offset and applying variant-specific translation at the final MMIO > access point. > 3. Removed ext_reg_sel, extend the CTI sysfs interface to expose banked > register instances on Qualcomm CTIs only. Numbered sysfs nodes are > hidden on standard ARM CTIs, and on Qualcomm CTIs their visibility is > derived from nr_trig_max (32 triggers per bank), ensuring that only > registers backed by hardware are exposed. > Link to v6 - https://lore.kernel.org/all/20251202-extended_cti-v6-0-ab68bb15c4f5@oss.qualcomm.com/ > > Changes in v6: > 1. Rename regs_idx to ext_reg_sel and add information in documentation > file. > 2. Reset CLAIMSET to zero for qcom-cti during probe. > 3. Retrieve idx value under spinlock. > 4. Use yearless copyright for qcom-cti.h. > Link to v5 - https://lore.kernel.org/all/20251020-extended_cti-v5-0-6f193da2d467@oss.qualcomm.com/ > > Changes in v5: > 1. Move common part in qcom-cti.h to coresight-cti.h. > 2. Convert trigger usage fields to dynamic bitmaps and arrays. > 3. Fix holes in struct cti_config to save some space. > 4. Revert the previous changes related to the claim tag in > cti_enable/disable_hw. > Link to v4 - https://lore.kernel.org/linux-arm-msm/20250902-extended_cti-v4-1-7677de04b416@oss.qualcomm.com/ > > Changes in v4: > 1. Read the DEVARCH registers to identify Qualcomm CTI. > 2. Add a reg_idx node, and refactor the coresight_cti_reg_show() and > coresight_cti_reg_store() functions accordingly. > 3. The register offsets specific to Qualcomm CTI are moved to qcom_cti.h. > Link to v3 - https://lore.kernel.org/linux-arm-msm/20250722081405.2947294-1-quic_jinlmao@quicinc.com/ > > Changes in v3: > 1. Rename is_extended_cti() to of_is_extended_cti(). > 2. Add the missing 'i' when write the CTI trigger registers. > 3. Convert the multi-line output in sysfs to single line. > 4. Initialize offset arrays using designated initializer. > Link to V2 - https://lore.kernel.org/all/20250429071841.1158315-3-quic_jinlmao@quicinc.com/ > > Changes in V2: > 1. Add enum for compatible items. > 2. Move offset arrays to coresight-cti-core > > Signed-off-by: Yingchao Deng > --- > Yingchao Deng (4): > coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays > coresight: cti: encode trigger register index in register offsets > coresight: cti: add Qualcomm extended CTI identification and quirks > coresight: cti: expose banked sysfs registers for Qualcomm extended CTI > > drivers/hwtracing/coresight/coresight-cti-core.c | 114 ++++++++++++++++----- > .../hwtracing/coresight/coresight-cti-platform.c | 16 +-- > drivers/hwtracing/coresight/coresight-cti-sysfs.c | 75 ++++++++++++-- > drivers/hwtracing/coresight/coresight-cti.h | 30 ++++-- > drivers/hwtracing/coresight/qcom-cti.h | 65 ++++++++++++ > 5 files changed, 247 insertions(+), 53 deletions(-) > --- > base-commit: 5bca1f031b65a4a8caf700537cbbc770252af475 > change-id: 20260324-extended_cti-707638ceee9e > > Best regards, Gentle reminder. thanks, Yingchao.