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[78.26.46.173]) by smtp.gmail.com with ESMTPSA id 27-20020ac25f5b000000b004896ed8dce3sm1448860lfz.2.2022.07.25.13.28.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 25 Jul 2022 13:28:12 -0700 (PDT) Message-ID: <979a618d-a107-af3d-c101-de6eb9e89464@linaro.org> Date: Mon, 25 Jul 2022 22:28:11 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.12.0 Subject: Re: [EXT] Re: [PATCH v3 3/4] dt-bindings: irqchip: imx mu work as msi controller Content-Language: en-US To: Frank Li , "jdmason@kudzu.us" , "maz@kernel.org" , "tglx@linutronix.de" , "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "shawnguo@kernel.org" , "s.hauer@pengutronix.de" , "kw@linux.com" , "bhelgaas@google.com" Cc: "kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-pci@vger.kernel.org" , Peng Fan , Aisheng Dong , "kernel@pengutronix.de" , "festevam@gmail.com" , dl-linux-imx , "kishon@ti.com" , "lorenzo.pieralisi@arm.com" , "ntb@lists.linux.dev" References: <20220720213036.1738628-1-Frank.Li@nxp.com> <20220720213036.1738628-4-Frank.Li@nxp.com> <2c11d0b0-b012-ea24-5c3c-305bbdd231a0@linaro.org> <7994d7c7-ae13-a136-f60c-40fd9918565d@linaro.org> From: Krzysztof Kozlowski In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220725_132815_500427_AA2C3534 X-CRM114-Status: GOOD ( 10.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 25/07/2022 18:55, Frank Li wrote: >>>> Not minItems but maxItems in general, but anyway you need to actually >>>> list and describe the items (and then skip min/max) >>> [Frank Li] >>> I am not sure format. Any example? >>> >>> Reg: >>> Items: >>> - description: a side register >>> - description: b side register >> >> Yes, but then explain what is A and B in bindings description. > > [Frank Li] How about "A(B) side base register address." > Any other description need? In top-level description you have: "The MU also provides the ability for one processor to signal the other processor using interrupts." so maybe: "The MU also provides the ability for one processor (A side) to signal the other processor (B side) using interrupts." > >> >> Why MU, which sits on A side needs to access other side (B) registers? > > [Frank Li] MU work as MSI controller for PCI EP. So driver need provide > B side register to PCI EP by msi_msg. PCI EP driver use this address to set > PCI bar. Then PCI host can write this address to trigger PCIe EP side irq > As doorbell. > > MU MSI driver also need A side register > To get irq status. So MU MSI need both side registers. OK. Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel