From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3BE15CF31A9 for ; Wed, 2 Oct 2024 10:00:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: Content-Type:In-Reply-To:From:References:Cc:To:Subject:MIME-Version:Date: Message-ID:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=jtaWLvTh3KNR4zVE1XPSbWTPJ/daeW1JwdntnD7k2Lo=; b=yb3vXRvf2jeimrKJq/u9PXX7Nb yWmb7W4qLzqmBlb4yLmeG28P2qFl35nHW+FXO/reoChBwMb9PMtNTaesZoTbgOmAzfBY+p8EOHuXI 5FRdBAcsshUO/ti3HzBswwuV71UtEuWGbiViTgEdtkHX2cWNa8MvRgul7q30DOyDearKi9bZAyWXv dBu1xpUDm3B2K2qB3rDAzekMaNm5qKmMrCqxsI4//zRFlmt3GHmgWe3M+9A3ILtLASVG1yYANG9ZK cC3Ame3qxjSbA2HCLy/rHzNzXVGYe+eDlj9TtiTQu21aBiRn98eEtrvMKRTjdl4qZM3G8VlcC6Kpc mmk0FI0A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1svw9i-00000005QAA-22Ak; Wed, 02 Oct 2024 10:00:26 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98 #2 (Red Hat Linux)) id 1svw8U-00000005Q20-0YhT for linux-arm-kernel@lists.infradead.org; Wed, 02 Oct 2024 09:59:11 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2B724339; Wed, 2 Oct 2024 02:59:37 -0700 (PDT) Received: from [10.57.75.246] (unknown [10.57.75.246]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8FEA43F587; Wed, 2 Oct 2024 02:59:06 -0700 (PDT) Message-ID: <99cee26b-351e-4bc3-81a8-ec8ced373770@arm.com> Date: Wed, 2 Oct 2024 10:59:04 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] iommu/arm-smmu-v3: Fix L1 stream table index calculation for AmpereOne To: Yang Shi , Nicolin Chen Cc: jgg@ziepe.ca, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20241001180346.1485194-1-yang@os.amperecomputing.com> <45b97496-29a2-4111-ba38-3c8bcf9f8b4d@os.amperecomputing.com> <742bd6d6-9d25-4f8c-9574-3d39a91c89cb@os.amperecomputing.com> From: Robin Murphy Content-Language: en-GB In-Reply-To: <742bd6d6-9d25-4f8c-9574-3d39a91c89cb@os.amperecomputing.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20241002_025910_237658_CA26BD3E X-CRM114-Status: GOOD ( 16.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2024-10-01 8:48 pm, Yang Shi wrote: > > > On 10/1/24 12:29 PM, Nicolin Chen wrote: >> On Tue, Oct 01, 2024 at 12:09:03PM -0700, Yang Shi wrote: >>> On 10/1/24 11:27 AM, Nicolin Chen wrote: >>>> On Tue, Oct 01, 2024 at 11:03:46AM -0700, Yang Shi wrote: >>>>> Using 64 bit immediate when doing shift can solve the problem.  The >>>>> disssembly after the fix looks like: >>>> [...] >>>> >>>>>           unsigned int last_sid_idx = >>>>> -               arm_smmu_strtab_l1_idx((1 << smmu->sid_bits) - 1); >>>>> +               arm_smmu_strtab_l1_idx((1UL << smmu->sid_bits) - 1); >>>> Could a 32-bit build be a corner case where UL is no longer a >>>> "64 bit" stated in the commit message? >>> It shouldn't. Because smmu v3 depends on ARM64. >>> >>> config ARM_SMMU_V3 >>>          tristate "ARM Ltd. System MMU Version 3 (SMMUv3) Support" >>>          depends on ARM64 >> ARM64 can have aarch32 support. I am not sure if ARM64 running a >> 32-bit OS can be a case though, (and not confined to AmpereOne). > > I don't think ARM64 runs 32-bit kernel, at least for newer kernel. Just use ULL - if the point is that it must be a 64-bit shift for correctness, then being clear about that intent is far more valuable than saving one character of source code. Thanks, Robin. > >> >>>> Then, can ssid_bits/s1cdmax be a concern similarly? >>> IIUC, ssid_bits is determined by IDR1_SSIDSIZE. It is GENMASK(10, 6). So >>> it shouldn't be 32. IDR1_SIDSIZE is GENMASK(5, 0). >> Rechecked the RM. Yea, max sid can be 32 but max ssid is 20 at >> this moment, so we should be safe. >> >> Thanks >> Nicolin >