[PATCH 0/3] mmc: sunxi: Fix MMC DDR modes for Allwinner A80

[PATCH 0/3] mmc: sunxi: Fix MMC DDR modes for Allwinner A80

[Chen-Yu Tsai]

Hi everyone,

This series fixes and re-enables eMMC HS-DDR support for Allwinner A80 SoC.
The issue with the original code was the mmc clock timings were incorrect,
and thus we had disabled HS-DDR on A80 for the previous release.

Patch 1 is a fix for mmc core. Arnd's patch to remove IS_ERR_VALUE replaced
it with an incorrect check on return values, thus blocking the code path
for HS-DDR and higher timing modes. This patch instead checks for a positive
return code, which is how mmc_select_bus_width indicates a success.

Patch 2 fixes the HS-DDR clock timings for the A80.

Patch 3 re-enables HS-DDR mode for the A80.


Regards
ChenYu

Chen-Yu Tsai (3):
  mmc: fix mmc mode selection for HS-DDR and higher
  mmc: sunxi: Fix DDR MMC timings for A80
  mmc: sunxi: Re-enable eMMC HS-DDR modes on Allwinner A80

 drivers/mmc/core/mmc.c       | 4 ++--
 drivers/mmc/host/sunxi-mmc.c | 9 ++-------
 2 files changed, 4 insertions(+), 9 deletions(-)

-- 
2.8.1

[PATCH 1/3] mmc: fix mmc mode selection for HS-DDR and higher

[Chen-Yu Tsai]

When IS_ERR_VALUE was removed from the mmc core code, it was replaced
with a simple not-zero check. This does not work, as the value checked
is the return value for mmc_select_bus_width, which returns the set
bit width on success. This made eMMC modes higher than HS-DDR unusable.

Fix this by checking for a positive return value instead.

Fixes: 287980e49ffc ("remove lots of IS_ERR_VALUE abuses")
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/mmc/core/mmc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index c984321d1881..aafb73d080ca 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -1276,7 +1276,7 @@ static int mmc_select_hs200(struct mmc_card *card)
 	 * switch to HS200 mode if bus width is set successfully.
 	 */
 	err = mmc_select_bus_width(card);
-	if (!err) {
+	if (err > 0) {
 		val = EXT_CSD_TIMING_HS200 |
 		      card->drive_strength << EXT_CSD_DRV_STR_SHIFT;
 		err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
@@ -1583,7 +1583,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
 	} else if (mmc_card_hs(card)) {
 		/* Select the desired bus width optionally */
 		err = mmc_select_bus_width(card);
-		if (!err) {
+		if (err > 0) {
 			err = mmc_select_hs_ddr(card);
 			if (err)
 				goto free_card;
-- 
2.8.1

[PATCH 1/3] mmc: fix mmc mode selection for HS-DDR and higher

[Krzysztof Kozlowski]

On Sun, May 29, 2016 at 9:04 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> When IS_ERR_VALUE was removed from the mmc core code, it was replaced
> with a simple not-zero check. This does not work, as the value checked
> is the return value for mmc_select_bus_width, which returns the set
> bit width on success. This made eMMC modes higher than HS-DDR unusable.
>
> Fix this by checking for a positive return value instead.
>
> Fixes: 287980e49ffc ("remove lots of IS_ERR_VALUE abuses")
> Cc: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  drivers/mmc/core/mmc.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>

Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>

Could you be so kind and pick it up as fast as possible for current
RC? Half of my boards fail (because they work on eMMC) so testing
patches before applying is limited.

Best regards,
Krzysztof

[PATCH 1/3] mmc: fix mmc mode selection for HS-DDR and higher

[Jaehoon Chung]

On 05/29/2016 04:04 PM, Chen-Yu Tsai wrote:
> When IS_ERR_VALUE was removed from the mmc core code, it was replaced
> with a simple not-zero check. This does not work, as the value checked
> is the return value for mmc_select_bus_width, which returns the set
> bit width on success. This made eMMC modes higher than HS-DDR unusable.
> 
> Fix this by checking for a positive return value instead.
> 
> Fixes: 287980e49ffc ("remove lots of IS_ERR_VALUE abuses")
> Cc: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Acked-by: Jaehoon Chung <jh80.chung@samsung.com>

Best Regards,
Jaehoon Chung

> ---
>  drivers/mmc/core/mmc.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
> index c984321d1881..aafb73d080ca 100644
> --- a/drivers/mmc/core/mmc.c
> +++ b/drivers/mmc/core/mmc.c
> @@ -1276,7 +1276,7 @@ static int mmc_select_hs200(struct mmc_card *card)
>  	 * switch to HS200 mode if bus width is set successfully.
>  	 */
>  	err = mmc_select_bus_width(card);
> -	if (!err) {
> +	if (err > 0) {
>  		val = EXT_CSD_TIMING_HS200 |
>  		      card->drive_strength << EXT_CSD_DRV_STR_SHIFT;
>  		err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
> @@ -1583,7 +1583,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
>  	} else if (mmc_card_hs(card)) {
>  		/* Select the desired bus width optionally */
>  		err = mmc_select_bus_width(card);
> -		if (!err) {
> +		if (err > 0) {
>  			err = mmc_select_hs_ddr(card);
>  			if (err)
>  				goto free_card;
> 

[PATCH 1/3] mmc: fix mmc mode selection for HS-DDR and higher

[Shawn Lin]

On 2016/5/29 15:04, Chen-Yu Tsai wrote:
> When IS_ERR_VALUE was removed from the mmc core code, it was replaced
> with a simple not-zero check. This does not work, as the value checked
> is the return value for mmc_select_bus_width, which returns the set
> bit width on success. This made eMMC modes higher than HS-DDR unusable.
>
> Fix this by checking for a positive return value instead.

Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>

>
> Fixes: 287980e49ffc ("remove lots of IS_ERR_VALUE abuses")
> Cc: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  drivers/mmc/core/mmc.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
> index c984321d1881..aafb73d080ca 100644
> --- a/drivers/mmc/core/mmc.c
> +++ b/drivers/mmc/core/mmc.c
> @@ -1276,7 +1276,7 @@ static int mmc_select_hs200(struct mmc_card *card)
>  	 * switch to HS200 mode if bus width is set successfully.
>  	 */
>  	err = mmc_select_bus_width(card);
> -	if (!err) {
> +	if (err > 0) {
>  		val = EXT_CSD_TIMING_HS200 |
>  		      card->drive_strength << EXT_CSD_DRV_STR_SHIFT;
>  		err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
> @@ -1583,7 +1583,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
>  	} else if (mmc_card_hs(card)) {
>  		/* Select the desired bus width optionally */
>  		err = mmc_select_bus_width(card);
> -		if (!err) {
> +		if (err > 0) {
>  			err = mmc_select_hs_ddr(card);
>  			if (err)
>  				goto free_card;
>


-- 
Best Regards
Shawn Lin

[PATCH 1/3] mmc: fix mmc mode selection for HS-DDR and higher

[Marcel Ziswiler]

On Sun, 2016-05-29 at 15:04 +0800, Chen-Yu Tsai wrote:
> When IS_ERR_VALUE was removed from the mmc core code, it was replaced
> with a simple not-zero check. This does not work, as the value
> checked
> is the return value for mmc_select_bus_width, which returns the set
> bit width on success. This made eMMC modes higher than HS-DDR
> unusable.
> 
> Fix this by checking for a positive return value instead.
> 
> Fixes: 287980e49ffc ("remove lots of IS_ERR_VALUE abuses")
> Cc: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

This fixes the following eMMC issue as experienced on Apalis T30 as
well:

[????7.194625] mmc1: mmc_select_hs200 failed, error 3
[????7.201549] mmc1: error 3 whilst initialising MMC card

Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>

> ---
> ?drivers/mmc/core/mmc.c | 4 ++--
> ?1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
> index c984321d1881..aafb73d080ca 100644
> --- a/drivers/mmc/core/mmc.c
> +++ b/drivers/mmc/core/mmc.c
> @@ -1276,7 +1276,7 @@ static int mmc_select_hs200(struct mmc_card
> *card)
> ?	?* switch to HS200 mode if bus width is set successfully.
> ?	?*/
> ?	err = mmc_select_bus_width(card);
> -	if (!err) {
> +	if (err > 0) {
> ?		val = EXT_CSD_TIMING_HS200 |
> ?		??????card->drive_strength << EXT_CSD_DRV_STR_SHIFT;
> ?		err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
> @@ -1583,7 +1583,7 @@ static int mmc_init_card(struct mmc_host *host,
> u32 ocr,
> ?	} else if (mmc_card_hs(card)) {
> ?		/* Select the desired bus width optionally */
> ?		err = mmc_select_bus_width(card);
> -		if (!err) {
> +		if (err > 0) {
> ?			err = mmc_select_hs_ddr(card);
> ?			if (err)
> ?				goto free_card;

[PATCH 1/3] mmc: fix mmc mode selection for HS-DDR and higher

[Bjorn Andersson]

On Sun, May 29, 2016 at 12:04 AM, Chen-Yu Tsai <wens@csie.org> wrote:
> When IS_ERR_VALUE was removed from the mmc core code, it was replaced
> with a simple not-zero check. This does not work, as the value checked
> is the return value for mmc_select_bus_width, which returns the set
> bit width on success. This made eMMC modes higher than HS-DDR unusable.
>
> Fix this by checking for a positive return value instead.

mmc_select_bus_width() can return 0 on "success" as well and the
previous check was !IS_ERR_VALUE(err), which coverts that. So I
believe these checks should be for err >= 0 rather than just > 0.


Either way this fixes the boot failures seen on my Qualcomm based
boards with v4.7-rc1.

Regards,
Bjorn

[PATCH 1/3] mmc: fix mmc mode selection for HS-DDR and higher

[Chen-Yu Tsai]

On Thu, Jun 2, 2016 at 2:58 AM, Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
> On Sun, May 29, 2016 at 12:04 AM, Chen-Yu Tsai <wens@csie.org> wrote:
>> When IS_ERR_VALUE was removed from the mmc core code, it was replaced
>> with a simple not-zero check. This does not work, as the value checked
>> is the return value for mmc_select_bus_width, which returns the set
>> bit width on success. This made eMMC modes higher than HS-DDR unusable.
>>
>> Fix this by checking for a positive return value instead.
>
> mmc_select_bus_width() can return 0 on "success" as well and the
> previous check was !IS_ERR_VALUE(err), which coverts that. So I
> believe these checks should be for err >= 0 rather than just > 0.

>From the comments above the function:
"Zero is returned instead of error value if the wide width is not supported."

The documents I found, which were more vendor datasheets, only list
bit widths 4 and 8 for high speed SDR/DDR and HS200.

Not sure what the MMC spec actually says though, as I do not have
it.

Regards
ChenYu

>
>
> Either way this fixes the boot failures seen on my Qualcomm based
> boards with v4.7-rc1.
>
> Regards,
> Bjorn

[PATCH 1/3] mmc: fix mmc mode selection for HS-DDR and higher

[Ulf Hansson]

+ Linus

On 29 May 2016 at 09:04, Chen-Yu Tsai <wens@csie.org> wrote:
> When IS_ERR_VALUE was removed from the mmc core code, it was replaced
> with a simple not-zero check. This does not work, as the value checked
> is the return value for mmc_select_bus_width, which returns the set
> bit width on success. This made eMMC modes higher than HS-DDR unusable.
>
> Fix this by checking for a positive return value instead.
>
> Fixes: 287980e49ffc ("remove lots of IS_ERR_VALUE abuses")
> Cc: Arnd Bergmann <arnd@arndb.de>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  drivers/mmc/core/mmc.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
> index c984321d1881..aafb73d080ca 100644
> --- a/drivers/mmc/core/mmc.c
> +++ b/drivers/mmc/core/mmc.c
> @@ -1276,7 +1276,7 @@ static int mmc_select_hs200(struct mmc_card *card)
>          * switch to HS200 mode if bus width is set successfully.
>          */
>         err = mmc_select_bus_width(card);
> -       if (!err) {
> +       if (err > 0) {
>                 val = EXT_CSD_TIMING_HS200 |
>                       card->drive_strength << EXT_CSD_DRV_STR_SHIFT;
>                 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
> @@ -1583,7 +1583,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
>         } else if (mmc_card_hs(card)) {
>                 /* Select the desired bus width optionally */
>                 err = mmc_select_bus_width(card);
> -               if (!err) {
> +               if (err > 0) {

As pointed out in the review by Bj?rn, to restore the old behaviour we
should check for "err >= 0".
No need to send a new patch, I can amend the current version.

>                         err = mmc_select_hs_ddr(card);
>                         if (err)
>                                 goto free_card;
> --
> 2.8.1
>

Finally, I am a little concerned about the commit 287980e49ffc
("remove lots of IS_ERR_VALUE abuses") which introduced this
regression.

Surprisingly the IS_ERR_VALUE():s aren't being replaced by equivalent
checks, so perhaps there a more regressions. Moreover, I wonder why I
wasn't being on cc/to list when this patch was submitted a few days
ago, perhaps my review could prevented the regression from even
happen.

Anyway, let's fix this now! I will pick up $subject patch as fix asap...

and Arnd, can you please double-check that the commit 287980e49ffc
doesn?t seems to regress anything else!?

Kind regards
Uffe

[PATCH 1/3] mmc: fix mmc mode selection for HS-DDR and higher

[Krzysztof Kozlowski]

On Thu, Jun 2, 2016 at 10:31 AM, Ulf Hansson <ulf.hansson@linaro.org> wrote:
> + Linus
>
> On 29 May 2016 at 09:04, Chen-Yu Tsai <wens@csie.org> wrote:
>> When IS_ERR_VALUE was removed from the mmc core code, it was replaced
>> with a simple not-zero check. This does not work, as the value checked
>> is the return value for mmc_select_bus_width, which returns the set
>> bit width on success. This made eMMC modes higher than HS-DDR unusable.
>>
>> Fix this by checking for a positive return value instead.
>>
>> Fixes: 287980e49ffc ("remove lots of IS_ERR_VALUE abuses")
>> Cc: Arnd Bergmann <arnd@arndb.de>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>  drivers/mmc/core/mmc.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
>> index c984321d1881..aafb73d080ca 100644
>> --- a/drivers/mmc/core/mmc.c
>> +++ b/drivers/mmc/core/mmc.c
>> @@ -1276,7 +1276,7 @@ static int mmc_select_hs200(struct mmc_card *card)
>>          * switch to HS200 mode if bus width is set successfully.
>>          */
>>         err = mmc_select_bus_width(card);
>> -       if (!err) {
>> +       if (err > 0) {
>>                 val = EXT_CSD_TIMING_HS200 |
>>                       card->drive_strength << EXT_CSD_DRV_STR_SHIFT;
>>                 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
>> @@ -1583,7 +1583,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
>>         } else if (mmc_card_hs(card)) {
>>                 /* Select the desired bus width optionally */
>>                 err = mmc_select_bus_width(card);
>> -               if (!err) {
>> +               if (err > 0) {
>
> As pointed out in the review by Bj?rn, to restore the old behaviour we
> should check for "err >= 0".
> No need to send a new patch, I can amend the current version.
>
>>                         err = mmc_select_hs_ddr(card);
>>                         if (err)
>>                                 goto free_card;
>> --
>> 2.8.1
>>
>
> Finally, I am a little concerned about the commit 287980e49ffc
> ("remove lots of IS_ERR_VALUE abuses") which introduced this
> regression.
>
> Surprisingly the IS_ERR_VALUE():s aren't being replaced by equivalent
> checks, so perhaps there a more regressions. Moreover, I wonder why I
> wasn't being on cc/to list when this patch was submitted a few days
> ago, perhaps my review could prevented the regression from even
> happen.
>
> Anyway, let's fix this now! I will pick up $subject patch as fix asap...
>
> and Arnd, can you please double-check that the commit 287980e49ffc
> doesn?t seems to regress anything else!?

If only the 287980e49ffc could sit in linux-next for few days before
reaching v4.7-rc1... Could you please pick up the fix soon? Maybe
directly by Linus?

Best regards,
Krzysztof

[PATCH 1/3] mmc: fix mmc mode selection for HS-DDR and higher

[Ulf Hansson]

On 2 June 2016 at 11:35, Krzysztof Kozlowski <k.kozlowski@samsung.com> wrote:
> On Thu, Jun 2, 2016 at 10:31 AM, Ulf Hansson <ulf.hansson@linaro.org> wrote:
>> + Linus
>>
>> On 29 May 2016 at 09:04, Chen-Yu Tsai <wens@csie.org> wrote:
>>> When IS_ERR_VALUE was removed from the mmc core code, it was replaced
>>> with a simple not-zero check. This does not work, as the value checked
>>> is the return value for mmc_select_bus_width, which returns the set
>>> bit width on success. This made eMMC modes higher than HS-DDR unusable.
>>>
>>> Fix this by checking for a positive return value instead.
>>>
>>> Fixes: 287980e49ffc ("remove lots of IS_ERR_VALUE abuses")
>>> Cc: Arnd Bergmann <arnd@arndb.de>
>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>>> ---
>>>  drivers/mmc/core/mmc.c | 4 ++--
>>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
>>> index c984321d1881..aafb73d080ca 100644
>>> --- a/drivers/mmc/core/mmc.c
>>> +++ b/drivers/mmc/core/mmc.c
>>> @@ -1276,7 +1276,7 @@ static int mmc_select_hs200(struct mmc_card *card)
>>>          * switch to HS200 mode if bus width is set successfully.
>>>          */
>>>         err = mmc_select_bus_width(card);
>>> -       if (!err) {
>>> +       if (err > 0) {
>>>                 val = EXT_CSD_TIMING_HS200 |
>>>                       card->drive_strength << EXT_CSD_DRV_STR_SHIFT;
>>>                 err = __mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
>>> @@ -1583,7 +1583,7 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
>>>         } else if (mmc_card_hs(card)) {
>>>                 /* Select the desired bus width optionally */
>>>                 err = mmc_select_bus_width(card);
>>> -               if (!err) {
>>> +               if (err > 0) {
>>
>> As pointed out in the review by Bj?rn, to restore the old behaviour we
>> should check for "err >= 0".
>> No need to send a new patch, I can amend the current version.
>>
>>>                         err = mmc_select_hs_ddr(card);
>>>                         if (err)
>>>                                 goto free_card;
>>> --
>>> 2.8.1
>>>
>>
>> Finally, I am a little concerned about the commit 287980e49ffc
>> ("remove lots of IS_ERR_VALUE abuses") which introduced this
>> regression.
>>
>> Surprisingly the IS_ERR_VALUE():s aren't being replaced by equivalent
>> checks, so perhaps there a more regressions. Moreover, I wonder why I
>> wasn't being on cc/to list when this patch was submitted a few days
>> ago, perhaps my review could prevented the regression from even
>> happen.
>>
>> Anyway, let's fix this now! I will pick up $subject patch as fix asap...
>>
>> and Arnd, can you please double-check that the commit 287980e49ffc
>> doesn?t seems to regress anything else!?
>
> If only the 287980e49ffc could sit in linux-next for few days before
> reaching v4.7-rc1... Could you please pick up the fix soon? Maybe
> directly by Linus?

The fix has already been applied and published through my mmc tree. I
am waiting for reports from kernelci, assuming those will be okay, I
will send a PR tomorrow so it should reach rc2.

Kind regards
Uffe

>
> Best regards,
> Krzysztof

[PATCH 2/3] mmc: sunxi: Fix DDR MMC timings for A80

[Chen-Yu Tsai]

The MMC clock timings were incorrectly calculated, when the conversion
from delay value to delay phase was done.

The 50M DDR and 50M DDR 8bit timings are off, and make eMMC DDR
unusable. Unfortunately it seems different controllers on the same SoC
have different timings. The new settings are taken from mmc2, which is
commonly used with eMMC.

The settings for the slower timing modes seem to work despite being
wrong, so leave them be.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/mmc/host/sunxi-mmc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 7fc8b7aa83f0..5873dc344ab2 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -970,8 +970,8 @@ static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
 	[SDXC_CLK_400K]		= { .output = 180, .sample = 180 },
 	[SDXC_CLK_25M]		= { .output = 180, .sample =  75 },
 	[SDXC_CLK_50M]		= { .output = 150, .sample = 120 },
-	[SDXC_CLK_50M_DDR]	= { .output =  90, .sample = 120 },
-	[SDXC_CLK_50M_DDR_8BIT]	= { .output =  90, .sample = 120 },
+	[SDXC_CLK_50M_DDR]	= { .output =  54, .sample =  36 },
+	[SDXC_CLK_50M_DDR_8BIT]	= { .output =  72, .sample =  72 },
 };
 
 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
-- 
2.8.1

[PATCH 2/3] mmc: sunxi: Fix DDR MMC timings for A80

[Hans de Goede]

Hi,

On 29-05-16 09:04, Chen-Yu Tsai wrote:
> The MMC clock timings were incorrectly calculated, when the conversion
> from delay value to delay phase was done.
>
> The 50M DDR and 50M DDR 8bit timings are off, and make eMMC DDR
> unusable. Unfortunately it seems different controllers on the same SoC
> have different timings. The new settings are taken from mmc2, which is
> commonly used with eMMC.

Hmm, I'm not really all that familiar with mmc, but can't an external
sdcard connected to mmc0 use DDR too ? Assuming the answer is yes, then
we really need to update the driver to use the right per controller
timings.

> The settings for the slower timing modes seem to work despite being
> wrong, so leave them be.

If you're sure the timings are wrong, please fix them. Sometimes wrong
timings do seem to work, but lead to unreliable communication, or turn
out to work on some boards and not on others due to routing differences.

Thanks & Regards,

Hans


>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
>  drivers/mmc/host/sunxi-mmc.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> index 7fc8b7aa83f0..5873dc344ab2 100644
> --- a/drivers/mmc/host/sunxi-mmc.c
> +++ b/drivers/mmc/host/sunxi-mmc.c
> @@ -970,8 +970,8 @@ static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = {
>  	[SDXC_CLK_400K]		= { .output = 180, .sample = 180 },
>  	[SDXC_CLK_25M]		= { .output = 180, .sample =  75 },
>  	[SDXC_CLK_50M]		= { .output = 150, .sample = 120 },
> -	[SDXC_CLK_50M_DDR]	= { .output =  90, .sample = 120 },
> -	[SDXC_CLK_50M_DDR_8BIT]	= { .output =  90, .sample = 120 },
> +	[SDXC_CLK_50M_DDR]	= { .output =  54, .sample =  36 },
> +	[SDXC_CLK_50M_DDR_8BIT]	= { .output =  72, .sample =  72 },
>  };
>
>  static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
>

[PATCH 2/3] mmc: sunxi: Fix DDR MMC timings for A80

[Chen-Yu Tsai]

On Mon, May 30, 2016 at 7:34 PM, Hans de Goede <hdegoede@redhat.com> wrote:
> Hi,
>
> On 29-05-16 09:04, Chen-Yu Tsai wrote:
>>
>> The MMC clock timings were incorrectly calculated, when the conversion
>> from delay value to delay phase was done.
>>
>> The 50M DDR and 50M DDR 8bit timings are off, and make eMMC DDR
>> unusable. Unfortunately it seems different controllers on the same SoC
>> have different timings. The new settings are taken from mmc2, which is
>> commonly used with eMMC.
>
>
> Hmm, I'm not really all that familiar with mmc, but can't an external
> sdcard connected to mmc0 use DDR too ? Assuming the answer is yes, then
> we really need to update the driver to use the right per controller
> timings.

I would very much like that to happen. However, SD card UHS-1 DDR modes
require 1.8V signaling, which is unavailable on _all_ sunxi boards.
This seems like a limit of most of the SoCs not having a separate IO
voltage rail for mmc pins.

Until then, I wouldn't worry that much.

>> The settings for the slower timing modes seem to work despite being
>> wrong, so leave them be.
>
>
> If you're sure the timings are wrong, please fix them. Sometimes wrong
> timings do seem to work, but lead to unreliable communication, or turn
> out to work on some boards and not on others due to routing differences.

Unfortunately I did try putting in the correct numbers for them, and my
eMMC then failed to probe. It seems the core switches up from 400kHz to
50MHz then to 50MHz DDR, and it fails somewhere in there, maybe at 50MHz.

I'm not sure if we need to add DT bindings to specify different delays
for different controllers, though. Seems like we'll never actually use
it.

Hope this answers your questions.

Regards
ChenYu

> Thanks & Regards,
>
> Hans
>
>
>
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>> ---
>>  drivers/mmc/host/sunxi-mmc.c | 4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
>> index 7fc8b7aa83f0..5873dc344ab2 100644
>> --- a/drivers/mmc/host/sunxi-mmc.c
>> +++ b/drivers/mmc/host/sunxi-mmc.c
>> @@ -970,8 +970,8 @@ static const struct sunxi_mmc_clk_delay
>> sun9i_mmc_clk_delays[] = {
>>         [SDXC_CLK_400K]         = { .output = 180, .sample = 180 },
>>         [SDXC_CLK_25M]          = { .output = 180, .sample =  75 },
>>         [SDXC_CLK_50M]          = { .output = 150, .sample = 120 },
>> -       [SDXC_CLK_50M_DDR]      = { .output =  90, .sample = 120 },
>> -       [SDXC_CLK_50M_DDR_8BIT] = { .output =  90, .sample = 120 },
>> +       [SDXC_CLK_50M_DDR]      = { .output =  54, .sample =  36 },
>> +       [SDXC_CLK_50M_DDR_8BIT] = { .output =  72, .sample =  72 },
>>  };
>>
>>  static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
>>
>

[PATCH 2/3] mmc: sunxi: Fix DDR MMC timings for A80

[Chen-Yu Tsai]

On Mon, May 30, 2016 at 8:59 PM, Chen-Yu Tsai <wens@csie.org> wrote:
> On Mon, May 30, 2016 at 7:34 PM, Hans de Goede <hdegoede@redhat.com> wrote:
>> Hi,
>>
>> On 29-05-16 09:04, Chen-Yu Tsai wrote:
>>>
>>> The MMC clock timings were incorrectly calculated, when the conversion
>>> from delay value to delay phase was done.
>>>
>>> The 50M DDR and 50M DDR 8bit timings are off, and make eMMC DDR
>>> unusable. Unfortunately it seems different controllers on the same SoC
>>> have different timings. The new settings are taken from mmc2, which is
>>> commonly used with eMMC.
>>
>>
>> Hmm, I'm not really all that familiar with mmc, but can't an external
>> sdcard connected to mmc0 use DDR too ? Assuming the answer is yes, then
>> we really need to update the driver to use the right per controller
>> timings.
>
> I would very much like that to happen. However, SD card UHS-1 DDR modes
> require 1.8V signaling, which is unavailable on _all_ sunxi boards.
> This seems like a limit of most of the SoCs not having a separate IO
> voltage rail for mmc pins.
>
> Until then, I wouldn't worry that much.

P.S. I also tried the settings from mmc0 in Allwinner sources. They gave
horrible results ( < 5 MB/s read ) on my CC-A80, while my Optimus wasn't
really affected. I wonder if there's some kind of auto-retry mechanism
in the MMC controller, or driver?

ChenYu

>>> The settings for the slower timing modes seem to work despite being
>>> wrong, so leave them be.
>>
>>
>> If you're sure the timings are wrong, please fix them. Sometimes wrong
>> timings do seem to work, but lead to unreliable communication, or turn
>> out to work on some boards and not on others due to routing differences.
>
> Unfortunately I did try putting in the correct numbers for them, and my
> eMMC then failed to probe. It seems the core switches up from 400kHz to
> 50MHz then to 50MHz DDR, and it fails somewhere in there, maybe at 50MHz.
>
> I'm not sure if we need to add DT bindings to specify different delays
> for different controllers, though. Seems like we'll never actually use
> it.
>
> Hope this answers your questions.
>
> Regards
> ChenYu
>
>> Thanks & Regards,
>>
>> Hans
>>
>>
>>
>>>
>>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
>>> ---
>>>  drivers/mmc/host/sunxi-mmc.c | 4 ++--
>>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
>>> index 7fc8b7aa83f0..5873dc344ab2 100644
>>> --- a/drivers/mmc/host/sunxi-mmc.c
>>> +++ b/drivers/mmc/host/sunxi-mmc.c
>>> @@ -970,8 +970,8 @@ static const struct sunxi_mmc_clk_delay
>>> sun9i_mmc_clk_delays[] = {
>>>         [SDXC_CLK_400K]         = { .output = 180, .sample = 180 },
>>>         [SDXC_CLK_25M]          = { .output = 180, .sample =  75 },
>>>         [SDXC_CLK_50M]          = { .output = 150, .sample = 120 },
>>> -       [SDXC_CLK_50M_DDR]      = { .output =  90, .sample = 120 },
>>> -       [SDXC_CLK_50M_DDR_8BIT] = { .output =  90, .sample = 120 },
>>> +       [SDXC_CLK_50M_DDR]      = { .output =  54, .sample =  36 },
>>> +       [SDXC_CLK_50M_DDR_8BIT] = { .output =  72, .sample =  72 },
>>>  };
>>>
>>>  static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
>>>
>>

[PATCH 2/3] mmc: sunxi: Fix DDR MMC timings for A80

[Hans de Goede]

Hi,

On 30-05-16 14:59, Chen-Yu Tsai wrote:
> On Mon, May 30, 2016 at 7:34 PM, Hans de Goede <hdegoede@redhat.com> wrote:
>> Hi,
>>
>> On 29-05-16 09:04, Chen-Yu Tsai wrote:
>>>
>>> The MMC clock timings were incorrectly calculated, when the conversion
>>> from delay value to delay phase was done.
>>>
>>> The 50M DDR and 50M DDR 8bit timings are off, and make eMMC DDR
>>> unusable. Unfortunately it seems different controllers on the same SoC
>>> have different timings. The new settings are taken from mmc2, which is
>>> commonly used with eMMC.
>>
>>
>> Hmm, I'm not really all that familiar with mmc, but can't an external
>> sdcard connected to mmc0 use DDR too ? Assuming the answer is yes, then
>> we really need to update the driver to use the right per controller
>> timings.
>
> I would very much like that to happen. However, SD card UHS-1 DDR modes
> require 1.8V signaling, which is unavailable on _all_ sunxi boards.
> This seems like a limit of most of the SoCs not having a separate IO
> voltage rail for mmc pins.
>
> Until then, I wouldn't worry that much.
>
>>> The settings for the slower timing modes seem to work despite being
>>> wrong, so leave them be.
>>
>>
>> If you're sure the timings are wrong, please fix them. Sometimes wrong
>> timings do seem to work, but lead to unreliable communication, or turn
>> out to work on some boards and not on others due to routing differences.
>
> Unfortunately I did try putting in the correct numbers for them, and my
> eMMC then failed to probe. It seems the core switches up from 400kHz to
> 50MHz then to 50MHz DDR, and it fails somewhere in there, maybe at 50MHz.
>
> I'm not sure if we need to add DT bindings to specify different delays
> for different controllers, though. Seems like we'll never actually use
> it.
>
> Hope this answers your questions.

Yes that answers my questions, and with my questions answered, this series is:

Acked-by: Hans de Goede <hdegoede@redhat.com>

Regards,

Hans

[PATCH 3/3] mmc: sunxi: Re-enable eMMC HS-DDR modes on Allwinner A80

[Chen-Yu Tsai]

Now the the HS-DDR mode clock timings have been corrected, we can
re-enable these modes on the A80.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
 drivers/mmc/host/sunxi-mmc.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index 5873dc344ab2..2ee4c21ec55e 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -1129,11 +1129,6 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
 				  MMC_CAP_1_8V_DDR |
 				  MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ;
 
-	/* TODO MMC DDR is not working on A80 */
-	if (of_device_is_compatible(pdev->dev.of_node,
-				    "allwinner,sun9i-a80-mmc"))
-		mmc->caps &= ~MMC_CAP_1_8V_DDR;
-
 	ret = mmc_of_parse(mmc);
 	if (ret)
 		goto error_free_dma;
-- 
2.8.1