[PATCH 0/5] arm64: dts: Add Corstone1000-A320 platform

[PATCH 0/5] arm64: dts: Add Corstone1000-A320 platform

[Rob Herring (Arm)]

The Corstone1000-A320 is a new Corstone1000 variation with Cortex-A320 
cores and an Ethos-U85 NPU. This series adds the new compatible strings, 
restructures the .dtsi files to handle the common parts, and then adds 
the new Corstone1000-A320 FVP platform.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
---
Rob Herring (Arm) (5):
      dt-bindings: arm,corstone1000: Add "arm,corstone1000-a320-fvp"
      dt-bindings: npu: arm,ethos: Add "arm,corstone1000-ethos-u85"
      arm64: dts: arm/corstone1000: Move cpu nodes
      arm64: dts: arm/corstone1000: Move FVP peripherals to separate .dtsi
      arm64: dts: arm/corstone1000: Add corstone-1000-a320

 .../devicetree/bindings/arm/arm,corstone1000.yaml  | 15 ++--
 .../devicetree/bindings/npu/arm,ethos.yaml         |  2 +-
 arch/arm64/boot/dts/arm/Makefile                   |  1 +
 arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts  | 15 ++++
 arch/arm64/boot/dts/arm/corstone1000-a320.dtsi     | 91 ++++++++++++++++++++
 arch/arm64/boot/dts/arm/corstone1000-fvp.dts       | 96 ++++++++--------------
 ...{corstone1000-fvp.dts => corstone1000-fvp.dtsi} | 33 --------
 arch/arm64/boot/dts/arm/corstone1000-mps3.dts      | 13 +++
 arch/arm64/boot/dts/arm/corstone1000.dtsi          | 13 ---
 9 files changed, 167 insertions(+), 112 deletions(-)
---
base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
change-id: 20260123-dt-corstone1000-a320-dc5a7aa15fbe

Best regards,
--  
Rob Herring (Arm) <robh@kernel.org>

[PATCH 1/5] dt-bindings: arm,corstone1000: Add "arm,corstone1000-a320-fvp"

[Rob Herring (Arm)]

The Arm Corstone1000-A320 is a variation of the Corstone1000 with
Cortex-A320 cores and an Ethos-U85 NPU. An FVP for the platform is
available here[1].

[1] https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Platforms/IoT%20FVPs

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
---
 .../devicetree/bindings/arm/arm,corstone1000.yaml         | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml
index cff1cdaadb13..48ab3356e383 100644
--- a/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,corstone1000.yaml
@@ -15,11 +15,11 @@ description: |+
   provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
   processors.
 
-  Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
-  systems for M-Class (or other) processors for adding sensors, connectivity,
-  video, audio and machine learning at the edge System and security IPs to build
-  a secure SoC for a range of rich IoT applications, for example gateways, smart
-  cameras and embedded systems.
+  Support for Cortex‑A32, Cortex‑A35, Cortex‑A53 and Cortex-A320 processors.
+  Two expansion systems for M-Class (or other) processors for adding sensors,
+  connectivity, video, audio and machine learning at the edge System and
+  security IPs to build a secure SoC for a range of rich IoT applications, for
+  example gateways, smart cameras and embedded systems.
 
   Integrated Secure Enclave providing hardware Root of Trust and supporting
   seamless integration of the optional CryptoCell™-312 cryptographic
@@ -39,6 +39,11 @@ properties:
           implementation of this system. See ARM ecosystems FVP's.
         items:
           - const: arm,corstone1000-fvp
+      - description: Corstone1000-A320 FVP is the Fixed Virtual Platform
+          implementation of this system with Cortex-A320 cores and Ethos-U85
+          NPU. See ARM ecosystems FVP's.
+        items:
+          - const: arm,corstone1000-a320-fvp
 
 additionalProperties: true
 

-- 
2.51.0

Re: [PATCH 1/5] dt-bindings: arm,corstone1000: Add "arm,corstone1000-a320-fvp"

[Krzysztof Kozlowski]

On 20/03/2026 17:47, Rob Herring (Arm) wrote:
> The Arm Corstone1000-A320 is a variation of the Corstone1000 with
> Cortex-A320 cores and an Ethos-U85 NPU. An FVP for the platform is
> available here[1].
> 
> [1] https://developer.arm.com/Tools%20and%20Software/Fixed%20Virtual%20Platforms/IoT%20FVPs
> 
> Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
> ---

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

[PATCH 2/5] dt-bindings: npu: arm,ethos: Add "arm,corstone1000-ethos-u85"

[Rob Herring (Arm)]

The Corstone-1000-A320 platform contains an Ethos-U85 NPU. Add a
specific compatible for it.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
---
 Documentation/devicetree/bindings/npu/arm,ethos.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/npu/arm,ethos.yaml b/Documentation/devicetree/bindings/npu/arm,ethos.yaml
index 716c4997f976..d5a1fae4db9d 100644
--- a/Documentation/devicetree/bindings/npu/arm,ethos.yaml
+++ b/Documentation/devicetree/bindings/npu/arm,ethos.yaml
@@ -30,7 +30,7 @@ properties:
               - fsl,imx93-npu
           - const: arm,ethos-u65
       - items:
-          - {}
+          - const: arm,corstone1000-ethos-u85
           - const: arm,ethos-u85
 
   reg:

-- 
2.51.0

Re: [PATCH 2/5] dt-bindings: npu: arm,ethos: Add "arm,corstone1000-ethos-u85"

[Krzysztof Kozlowski]

On 20/03/2026 17:47, Rob Herring (Arm) wrote:
> The Corstone-1000-A320 platform contains an Ethos-U85 NPU. Add a
> specific compatible for it.
> 
> Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
> ---
>  Documentation/devicetree/bindings/npu/arm,ethos.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

[PATCH 3/5] arm64: dts: arm/corstone1000: Move cpu nodes

[Rob Herring (Arm)]

In preparation to add a new Corstone-1000 variation with different CPUs,
move the CPU nodes into the specific platforms and out of the common
corstone1000.dtsi.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
---
 arch/arm64/boot/dts/arm/corstone1000-fvp.dts  | 54 ++++++++++++++++-----------
 arch/arm64/boot/dts/arm/corstone1000-mps3.dts | 13 +++++++
 arch/arm64/boot/dts/arm/corstone1000.dtsi     | 13 -------
 3 files changed, 45 insertions(+), 35 deletions(-)

diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
index 66ba6b027193..e479c79c1ea7 100644
--- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
+++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
@@ -48,30 +48,40 @@ sdmmc1: mmc@50000000 {
 		clocks = <&smbclk>, <&refclk100mhz>;
 		clock-names = "smclk", "apb_pclk";
 	};
-};
+	cpus: cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
 
-&cpus {
-	cpu1: cpu@1 {
-		device_type = "cpu";
-		compatible = "arm,cortex-a35";
-		reg = <0x1>;
-		enable-method = "psci";
-		next-level-cache = <&L2_0>;
-	};
+		cpu: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0 0>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
 
-	cpu2: cpu@2 {
-		device_type = "cpu";
-		compatible = "arm,cortex-a35";
-		reg = <0x2>;
-		enable-method = "psci";
-		next-level-cache = <&L2_0>;
-	};
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0 0x1>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0 0x2>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
 
-	cpu3: cpu@3 {
-		device_type = "cpu";
-		compatible = "arm,cortex-a35";
-		reg = <0x3>;
-		enable-method = "psci";
-		next-level-cache = <&L2_0>;
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0 0x3>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
 	};
 };
diff --git a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts
index 10d265be0c02..adcfaf7c55b8 100644
--- a/arch/arm64/boot/dts/arm/corstone1000-mps3.dts
+++ b/arch/arm64/boot/dts/arm/corstone1000-mps3.dts
@@ -13,6 +13,19 @@ / {
 	model = "ARM Corstone1000 FPGA MPS3 board";
 	compatible = "arm,corstone1000-mps3";
 
+	cpus: cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a35";
+			reg = <0 0>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+	};
+
 	smsc: ethernet@4010000 {
 		compatible = "smsc,lan9220", "smsc,lan9115";
 		reg = <0x40100000 0x10000>;
diff --git a/arch/arm64/boot/dts/arm/corstone1000.dtsi b/arch/arm64/boot/dts/arm/corstone1000.dtsi
index f35a5c96f3da..4d57dc197918 100644
--- a/arch/arm64/boot/dts/arm/corstone1000.dtsi
+++ b/arch/arm64/boot/dts/arm/corstone1000.dtsi
@@ -21,19 +21,6 @@ chosen {
 		stdout-path = "serial0:115200n8";
 	};
 
-	cpus: cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu: cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-a35";
-			reg = <0>;
-			enable-method = "psci";
-			next-level-cache = <&L2_0>;
-		};
-	};
-
 	memory@88200000 {
 		device_type = "memory";
 		reg = <0x88200000 0x77e00000>;

-- 
2.51.0

[PATCH 4/5] arm64: dts: arm/corstone1000: Move FVP peripherals to separate .dtsi

[Rob Herring (Arm)]

The FVPs have a common set of peripherals specific to the FVP. Move
these to a separate .dtsi so they can be shared across FVP platforms.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
---
 arch/arm64/boot/dts/arm/corstone1000-fvp.dts  | 36 +---------------------
 arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi | 44 +++++++++++++++++++++++++++
 2 files changed, 45 insertions(+), 35 deletions(-)

diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
index e479c79c1ea7..fac0999b1901 100644
--- a/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
+++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dts
@@ -8,46 +8,12 @@
 /dts-v1/;
 
 #include "corstone1000.dtsi"
+#include "corstone1000-fvp.dtsi"
 
 / {
 	model = "ARM Corstone1000 FVP (Fixed Virtual Platform)";
 	compatible = "arm,corstone1000-fvp";
 
-	smsc: ethernet@4010000 {
-		compatible = "smsc,lan91c111";
-		reg = <0x40100000 0x10000>;
-		phy-mode = "mii";
-		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
-		reg-io-width = <2>;
-	};
-
-	vmmc_v3_3d: regulator-vmmc {
-		compatible = "regulator-fixed";
-		regulator-name = "vmmc_supply";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		regulator-always-on;
-	};
-
-	sdmmc0: mmc@40300000 {
-		compatible = "arm,pl18x", "arm,primecell";
-		reg = <0x40300000 0x1000>;
-		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
-		max-frequency = <12000000>;
-		vmmc-supply = <&vmmc_v3_3d>;
-		clocks = <&smbclk>, <&refclk100mhz>;
-		clock-names = "smclk", "apb_pclk";
-	};
-
-	sdmmc1: mmc@50000000 {
-		compatible = "arm,pl18x", "arm,primecell";
-		reg = <0x50000000 0x10000>;
-		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-		max-frequency = <12000000>;
-		vmmc-supply = <&vmmc_v3_3d>;
-		clocks = <&smbclk>, <&refclk100mhz>;
-		clock-names = "smclk", "apb_pclk";
-	};
 	cpus: cpus {
 		#address-cells = <2>;
 		#size-cells = <0>;
diff --git a/arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi b/arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi
new file mode 100644
index 000000000000..dc6d77446e8f
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/corstone1000-fvp.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2022, Linaro Limited. All rights reserved.
+ *
+ */
+
+/ {
+	smsc: ethernet@4010000 {
+		compatible = "smsc,lan91c111";
+		reg = <0x40100000 0x10000>;
+		phy-mode = "mii";
+		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+		reg-io-width = <2>;
+	};
+
+	vmmc_v3_3d: regulator-vmmc {
+		compatible = "regulator-fixed";
+		regulator-name = "vmmc_supply";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+	};
+
+	sdmmc0: mmc@40300000 {
+		compatible = "arm,pl18x", "arm,primecell";
+		reg = <0x40300000 0x1000>;
+		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+		max-frequency = <12000000>;
+		vmmc-supply = <&vmmc_v3_3d>;
+		clocks = <&smbclk>, <&refclk100mhz>;
+		clock-names = "smclk", "apb_pclk";
+	};
+
+	sdmmc1: mmc@50000000 {
+		compatible = "arm,pl18x", "arm,primecell";
+		reg = <0x50000000 0x10000>;
+		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+		max-frequency = <12000000>;
+		vmmc-supply = <&vmmc_v3_3d>;
+		clocks = <&smbclk>, <&refclk100mhz>;
+		clock-names = "smclk", "apb_pclk";
+	};
+};

-- 
2.51.0

[PATCH 5/5] arm64: dts: arm/corstone1000: Add corstone-1000-a320

[Rob Herring (Arm)]

The Corstone-1000-a320 is a Corstone-1000 derivative with Cortex-A320 cores,
GIC-600, and Ethos-U85 NPU.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
---
 arch/arm64/boot/dts/arm/Makefile                  |  1 +
 arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts | 15 ++++
 arch/arm64/boot/dts/arm/corstone1000-a320.dtsi    | 91 +++++++++++++++++++++++
 3 files changed, 107 insertions(+)

diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Makefile
index f30ee045dc95..fa035c68991a 100644
--- a/arch/arm64/boot/dts/arm/Makefile
+++ b/arch/arm64/boot/dts/arm/Makefile
@@ -7,4 +7,5 @@ dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += fvp-base-revc.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-fvp.dtb corstone1000-mps3.dtb
+dtb-$(CONFIG_ARCH_VEXPRESS) += corstone1000-a320-fvp.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += morello-sdp.dtb morello-fvp.dtb
diff --git a/arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts b/arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts
new file mode 100644
index 000000000000..0f72af78b5e1
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/corstone1000-a320-fvp.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2026, Arm Limited. All rights reserved.
+ *
+ */
+
+/dts-v1/;
+
+#include "corstone1000-a320.dtsi"
+#include "corstone1000-fvp.dtsi"
+
+/ {
+	model = "ARM Corstone1000-A320 FVP (Fixed Virtual Platform)";
+	compatible = "arm,corstone1000-a320-fvp";
+};
diff --git a/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi b/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi
new file mode 100644
index 000000000000..f0937914350c
--- /dev/null
+++ b/arch/arm64/boot/dts/arm/corstone1000-a320.dtsi
@@ -0,0 +1,91 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2026, Arm Limited. All rights reserved.
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "corstone1000.dtsi"
+
+/ {
+	interrupt-parent = <&gic>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus: cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a320";
+			reg = <0 0>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		cpu1: cpu@100 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a320";
+			reg = <0 0x100>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		cpu2: cpu@200 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a320";
+			reg = <0 0x200>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+
+		cpu3: cpu@300 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a320";
+			reg = <0 0x300>;
+			enable-method = "psci";
+			next-level-cache = <&L2_0>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	sram: sram@2400000 {
+		compatible = "mmio-sram";
+		reg = <0x02400000 0x200000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+	};
+
+	gic: interrupt-controller@1c000000 {
+		compatible = "arm,gic-v3";
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupt-controller;
+		reg = <0x1c000000 0x10000>,
+		      <0x1c040000 0x80000>;
+		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+
+	soc {
+		npu@1a050000 {
+			compatible = "arm,corstone1000-ethos-u85", "arm,ethos-u85";
+			reg = <0x1a050000 0x1400>;
+			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&refclk100mhz>, <&refclk100mhz>;
+			clock-names = "core", "apb";
+			sram = <&sram>;
+		};
+	};
+};

-- 
2.51.0

Re: [PATCH 0/5] arm64: dts: Add Corstone1000-A320 platform

[Sudeep Holla]

On Fri, 20 Mar 2026 11:47:13 -0500, Rob Herring (Arm) wrote:
> The Corstone1000-A320 is a new Corstone1000 variation with Cortex-A320
> cores and an Ethos-U85 NPU. This series adds the new compatible strings,
> restructures the .dtsi files to handle the common parts, and then adds
> the new Corstone1000-A320 FVP platform.

Applied to sudeep.holla/linux (for-next/juno/updates), thanks!

[1/5] dt-bindings: arm,corstone1000: Add "arm,corstone1000-a320-fvp"
      https://git.kernel.org/sudeep.holla/c/f9d162866f2f
[2/5] dt-bindings: npu: arm,ethos: Add "arm,corstone1000-ethos-u85"
      https://git.kernel.org/sudeep.holla/c/55de145c8ec2
[3/5] arm64: dts: arm/corstone1000: Move cpu nodes
      https://git.kernel.org/sudeep.holla/c/903528ac234a
[4/5] arm64: dts: arm/corstone1000: Move FVP peripherals to separate .dtsi
      https://git.kernel.org/sudeep.holla/c/9c3904f94fdb
[5/5] arm64: dts: arm/corstone1000: Add corstone-1000-a320
      https://git.kernel.org/sudeep.holla/c/87599f1843d3
--
Regards,
Sudeep