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Tue, 21 Jun 2022 17:38:54 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 15F0B10002A; Tue, 21 Jun 2022 17:38:54 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 0E1C122F7A2; Tue, 21 Jun 2022 17:38:54 +0200 (CEST) Received: from [10.252.18.52] (10.75.127.116) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2308.20; Tue, 21 Jun 2022 17:38:53 +0200 Message-ID: <9b43b142-e62c-d46b-8b42-449720682463@foss.st.com> Date: Tue, 21 Jun 2022 17:38:52 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1 Subject: Re: [PATCH 1/2] iio: adc: stm32-adc: make safe adc disable Content-Language: en-US To: Olivier Moysan , Alexandre Torgue , Jonathan Cameron , Lars-Peter Clausen , Maxime Coquelin , Paul Cercueil , Wan Jiabing CC: , , , References: <20220620154738.801706-1-olivier.moysan@foss.st.com> <20220620154738.801706-2-olivier.moysan@foss.st.com> From: Fabrice Gasnier In-Reply-To: <20220620154738.801706-2-olivier.moysan@foss.st.com> X-Originating-IP: [10.75.127.116] X-ClientProxiedBy: GPXDAG2NODE5.st.com (10.75.127.69) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.64.514 definitions=2022-06-21_08,2022-06-21_01,2022-02-23_01 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220621_083912_859875_BE5DCE4D X-CRM114-Status: GOOD ( 16.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 6/20/22 17:47, Olivier Moysan wrote: > From ADC reference manual the software is allowed to write the > control bit ADDIS of the ADC_CR register only if the ADC is enabled. > Return immediately from stm32h7_adc_disable() if ADC is already disabled. > > Signed-off-by: Olivier Moysan Hi Olivier, You can add my: Reviewed-by: Fabrice Gasnier Thanks, Fabrice > --- > drivers/iio/adc/stm32-adc.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c > index a68ecbda6480..80e333f65ddd 100644 > --- a/drivers/iio/adc/stm32-adc.c > +++ b/drivers/iio/adc/stm32-adc.c > @@ -876,6 +876,9 @@ static void stm32h7_adc_disable(struct iio_dev *indio_dev) > int ret; > u32 val; > > + if (!(stm32_adc_readl(adc, STM32H7_ADC_CR) & STM32H7_ADEN)) > + return; > + > /* Disable ADC and wait until it's effectively disabled */ > stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADDIS); > ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_CR, val, _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel