From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4DEC3C88E75 for ; Tue, 15 Sep 2026 11:58:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Cc:List-Subscribe: List-Help:List-Post:List-Archive:List-Unsubscribe:List-Id: Content-Transfer-Encoding:Content-Type:In-Reply-To:From:References:To:Subject :MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=Rad2O+IqRjmNXPtycSekPgyf57whSar6kjQ6VyBRet0=; b=qhWQfKlWbTGxe0 C9NZpIl17cmUdgj9/f2kubH3c8JypqapbP6g8liE9JOeWPywKw2tzVqqf385CrBA9+cC7wcN3pbA0 UAWrSh0yncwEN/MY2XogRDscZDfvOT270VVxFKrIUFVPq+aXTxvsHJIFp3BmvUO9NuF0OIwMNt3xf JUOxVIAK2F7s9PqmWcf1DYv+tpOrgXrEdFc0ZGyFlj7yxtK/LnBCm78R4ER4olP1p+REcIH+ZqqLP BEH+7FT+ddfQPn/YIVEzH48cJmO/Rt5YqbyR7uISMK/dlwk0hDXXMmy15R30E0+DkN8TePCpwlts3 +c92gc7keuhP66isURUQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1x6Ro8-00000006LOs-2H3H; Tue, 15 Sep 2026 11:58:40 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1x6Ro5-00000006LNi-38MR for linux-arm-kernel@lists.infradead.org; Tue, 15 Sep 2026 11:58:39 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2C4BD152B; Tue, 15 Sep 2026 04:58:31 -0700 (PDT) Received: from [10.0.152.207] (unknown [10.0.152.207]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C91AB3F882; Tue, 15 Sep 2026 04:58:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1789473514; bh=Fl+EgKkPkakLVisQpLonxhPcu+zwypBro/ejEUYfjrU=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=NA8i5q1EuHRbfztBTbIA+kVO+k57t0pj/9fAc4nHaoY1wrMY50wMP+Gmcqq6wIJdN lxnsqJrLT8eoCHOuYfbjtAb0OxdpyrW77k3yFNsokl+L3eRCjIM7l5xXxsrEyqUKDl T3OK/6wItGPV4/8PoYdU26m+Ex1ohryNOo0k4bMs= Message-ID: <9c10e82b-859e-4280-9485-706828f4a5e0@arm.com> Date: Tue, 15 Sep 2026 12:58:30 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 15/21] arm64: percpu: Implement preemptible read/write ops To: Mark Rutland , linux-arm-kernel@lists.infradead.org References: <20260908151741.394589-1-mark.rutland@arm.com> <20260908151741.394589-16-mark.rutland@arm.com> Content-Language: en-GB From: Vladimir Murzin In-Reply-To: <20260908151741.394589-16-mark.rutland@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260915_045837_886288_631B4E33 X-CRM114-Status: GOOD ( 18.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ryan.roberts@arm.com, usama.anjum@arm.com, peterz@infradead.org, catalin.marinas@arm.com, david.laight.linux@gmail.com, stable@vger.kernel.org, ruanjinjie@huawei.com, james.morse@arm.com, yang@os.amperecomputing.com, cl@gentwo.org, maz@kernel.org, david@kernel.org, ljs@kernel.org, will@kernel.org, ardb@kernel.org Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 9/8/26 16:17, Mark Rutland wrote: > Use the PCPU GPR infrastructure to implement preemptible this_cpu_read() > and this_cpu_write(). > > This change means that this_cpu_read() will always use a plain LDR, even > in LTO configurations where READ_ONCE() will use LDA[P]R. Using plain > LDR is preferable, given that the rationale for using LDA[P]R in > READ_ONCE() was to retain address dependencies against values written by > other CPUs, which isn't expected usage for this_cpu_read(). Using plain > LDR will enforce fewer ordering constraints. > > Test case: > > | void outline_this_cpu_write_u64(u64 __percpu *p, u64 v) > | { > | this_cpu_write(*p, v); > | } > > Generated code before this patch (v7.2-rc4): > > | : > | paciasp > | stp x29, x30, [sp, #-16]! > | mrs x2, sp_el0 > | mov x29, sp > | ldr w3, [x2, #8] > | add w3, w3, #0x1 > | str w3, [x2, #8] > | mrs x3, tpidr_el1 > | str x1, [x0, x3] > | ldr x0, [x2, #8] > | sub x0, x0, #0x1 > | str w0, [x2, #8] > | cbz x0, 1f > | ldr x0, [x2, #8] > | cbnz x0, 2f > | 1: bl preempt_schedule_notrace > | 2: ldp x29, x30, [sp], #16 > | autiasp > | ret > > Generated code after this patch: > > | : > | mrs x2, sp_el0 > | mov w3, #0x7c60 > | strh w3, [x2, #20] > | mrs x3, tpidr_el1 > | str x1, [x0, x3] > | strh wzr, [x2, #20] > | ret > > Signed-off-by: Mark Rutland > Tested-by: Muhammad Usama Anjum > Cc: Ada Couprie Diaz > Cc: Ard Biesheuvel > Cc: Catalin Marinas > Cc: James Morse > Cc: Jinjie Ruan > Cc: Marc Zyngier > Cc: Peter Zijlstra > Cc: Vladimir Murzin > Cc: Will Deacon > Cc: Yang Shi > --- > arch/arm64/include/asm/percpu.h | 79 ++++++++++++++++++++++++--------- > 1 file changed, 58 insertions(+), 21 deletions(-) > > diff --git a/arch/arm64/include/asm/percpu.h b/arch/arm64/include/asm/percpu.h > index 03fa916030fd1..984f69846cc09 100644 > --- a/arch/arm64/include/asm/percpu.h > +++ b/arch/arm64/include/asm/percpu.h > @@ -128,15 +128,42 @@ static inline unsigned long __kern_my_cpu_offset(void) > #define __my_cpu_offset __kern_my_cpu_offset() > #endif > > -#define PERCPU_RW_OPS(sz) \ > -static inline unsigned long __percpu_read_##sz(void *ptr) \ > -{ \ > - return READ_ONCE(*(u##sz *)ptr); \ > -} \ > - \ > -static inline void __percpu_write_##sz(void *ptr, unsigned long val) \ > -{ \ > - WRITE_ONCE(*(u##sz *)ptr, (u##sz)val); \ > +#define PERCPU_RW_OPS(w, sfx, sz) \ > +static inline unsigned long __percpu_read_##sz(void __percpu *pcp) \ > +{ \ > + u16 *gprs = ¤t_thread_info()->pcpu_gprs; \ > + unsigned long off; \ > + unsigned long val; \ > + \ > + asm volatile( \ > + __PCPU_GPRS_BEGIN_OFFSET("%[gprs]", "%[pcp]", "%[off]") \ > + " ldr" #sfx "\t%" #w "[val], [%[pcp], %[off]]\n" \ > + __PCPU_GPRS_END("%[gprs]") \ > + : [gprs] "=Qo" (*gprs), \ > + [off] "=&r" (off), \ > + [val] "=&r" (val) \ > + : [pcp] "r" (pcp) \ > + : "memory" \ > + ); \ > + \ > + return val; \ > +} \ > + \ > +static inline void __percpu_write_##sz(void __percpu *pcp, unsigned long val) \ > +{ \ > + u16 *gprs = ¤t_thread_info()->pcpu_gprs; \ > + unsigned long off; \ > + \ > + asm volatile( \ > + __PCPU_GPRS_BEGIN_OFFSET("%[gprs]", "%[pcp]", "%[off]") \ > + " str" #sfx "\t%" #w "[val], [%[pcp], %[off]]\n" \ > + __PCPU_GPRS_END("%[gprs]") \ > + : [gprs] "=Qo" (*gprs), \ > + [off] "=&r" (off) \ > + : [pcp] "r" (pcp), \ > + [val] "r" ((u##sz)val) \ > + : "memory" \ > + ); \ > } > > #define __PERCPU_OP_CASE(w, sfx, name, sz, op_llsc, op_lse) \ > @@ -196,10 +223,10 @@ __percpu_##name##_return_case_##sz(void *ptr, unsigned long val) \ > __PERCPU_RET_OP_CASE(w, , name, 32, op_llsc, op_lse) \ > __PERCPU_RET_OP_CASE( , , name, 64, op_llsc, op_lse) > > -PERCPU_RW_OPS(8) > -PERCPU_RW_OPS(16) > -PERCPU_RW_OPS(32) > -PERCPU_RW_OPS(64) > +PERCPU_RW_OPS(w, b, 8) > +PERCPU_RW_OPS(w, h, 16) > +PERCPU_RW_OPS(w, , 32) > +PERCPU_RW_OPS( , , 64) > > /* > * Use value-returning atomics for CPU-local ops as they are more likely > @@ -245,23 +272,33 @@ PERCPU_RET_OP(add, add, ldadd) > __retval; \ > }) > > +#define _pcp_wrap(op, pcp, ...) \ > +({ \ > + op(&(pcp), __VA_ARGS__); \ > +}) > + > +#define _pcp_wrap_return(op, pcp, args...) \ > +({ \ > + (typeof(pcp))op(&(pcp), ##args); \ > +}) > + > #define this_cpu_read_1(pcp) \ > - _pcp_protect_return(__percpu_read_8, pcp) > + _pcp_wrap_return(__percpu_read_8, pcp) > #define this_cpu_read_2(pcp) \ > - _pcp_protect_return(__percpu_read_16, pcp) > + _pcp_wrap_return(__percpu_read_16, pcp) > #define this_cpu_read_4(pcp) \ > - _pcp_protect_return(__percpu_read_32, pcp) > + _pcp_wrap_return(__percpu_read_32, pcp) > #define this_cpu_read_8(pcp) \ > - _pcp_protect_return(__percpu_read_64, pcp) > + _pcp_wrap_return(__percpu_read_64, pcp) > > #define this_cpu_write_1(pcp, val) \ > - _pcp_protect(__percpu_write_8, pcp, (unsigned long)(val)) > + _pcp_wrap(__percpu_write_8, pcp, (unsigned long)(val)) > #define this_cpu_write_2(pcp, val) \ > - _pcp_protect(__percpu_write_16, pcp, (unsigned long)(val)) > + _pcp_wrap(__percpu_write_16, pcp, (unsigned long)(val)) > #define this_cpu_write_4(pcp, val) \ > - _pcp_protect(__percpu_write_32, pcp, (unsigned long)(val)) > + _pcp_wrap(__percpu_write_32, pcp, (unsigned long)(val)) > #define this_cpu_write_8(pcp, val) \ > - _pcp_protect(__percpu_write_64, pcp, (unsigned long)(val)) > + _pcp_wrap(__percpu_write_64, pcp, (unsigned long)(val)) > > #define this_cpu_add_1(pcp, val) \ > _pcp_protect(__percpu_add_case_8, pcp, val) > -- 2.30.2 > FWIW, Reviewed-by: Vladimir Murzin