From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D9E2C4332F for ; Mon, 28 Nov 2022 18:30:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:Message-ID:References:In-Reply-To:Subject:Cc:To:From :Date:MIME-Version:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=SNdlA98B/6kuOaTBmkU3JASl2Fo+c0/ddo9x01E2dgk=; b=xKnDuzSX4T71U8eYGaOSbmKiCj eXZeT91A0ThViDuZRnLYu2by0xeefYFbM8YcPbueiDv73H5xSbHUFTzv4+DYDsCGFGhtqpF47exSD JgQenO1MN4GZq5NargccUBLAs14pnhf0A4pHSiMPp6g0ePw+BATdFxMctRkwpfeJTde5bswViRXEh OIjJ/RpVJShtg1tEHORweQ0GoJm+GLJbAHHrWDtEGRbdr/c4AgCaHY6u9dscaAPOGt+Ta94nhwskS E7DcnhUV5SKqFzKkTWrHO+BOxkwF7eg5JA0bSXN4rgH5ypsKT22YOiCvZTM5GeK+T1ivT3/0aE23R DTA7YGrg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ozit1-003bag-8n; Mon, 28 Nov 2022 18:29:47 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oziQK-003KkJ-Lp for linux-arm-kernel@lists.infradead.org; Mon, 28 Nov 2022 18:00:13 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C59806132D; Mon, 28 Nov 2022 18:00:07 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3301FC433C1; Mon, 28 Nov 2022 18:00:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1669658407; bh=fFqVm7Sp7CNTRKo7YVh6gmoGqz4wXJBZMO4CLCHZYD8=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=soyZ2u1NcsUhQnwN2NfCdn/DJAweb4JZU0yhvHg2K4LcpNqYdbpFlEN3wDYtCrtC8 exdsRLV1SHlsXL5XQtNtidh+HM2io/N8ZwgyhboGMj5VAJJMdWNlU9gket4UCn+4eM /gGuWMuLYmylBgiKLDD23xuCIFvt7wQ2M4uKDE6xx3u1mWChhxmvMfmm5JoZ9IjF76 D+LY9qfXu1toB0RVicjrV3vcN1X/QqgqhWc/G2Obq7ls23k7iggxbZeFon0qG5ZgJd Ycmhis11JiTg+VMYj8YKS7mz3jWHgplVR4152oOsYy6Kpy5C+a5ahF8KjD0wOfpJ11 RmSotlDeRKxsQ== Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1oziQH-009AqF-1u; Mon, 28 Nov 2022 18:00:05 +0000 MIME-Version: 1.0 Date: Mon, 28 Nov 2022 18:00:04 +0000 From: Marc Zyngier To: Ard Biesheuvel , Ryan Roberts Cc: linux-arm-kernel@lists.infradead.org, Will Deacon , Mark Rutland , Kees Cook , Catalin Marinas , Mark Brown , Anshuman Khandual , Richard Henderson Subject: Re: [PATCH v2 12/19] arm64: mm: Add definitions to support 5 levels of paging In-Reply-To: References: <20221124123932.2648991-1-ardb@kernel.org> <20221124123932.2648991-13-ardb@kernel.org> <6f0cc4a8-a58d-e715-3078-5b8ccc288c2e@arm.com> User-Agent: Roundcube Webmail/1.4.13 Message-ID: <9c6b149f78cf5f0739b9ce6760cc2e6a@kernel.org> X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: ardb@kernel.org, ryan.roberts@arm.com, linux-arm-kernel@lists.infradead.org, will@kernel.org, mark.rutland@arm.com, keescook@chromium.org, catalin.marinas@arm.com, broonie@kernel.org, anshuman.khandual@arm.com, richard.henderson@linaro.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221128_100008_840807_FD5A1878 X-CRM114-Status: GOOD ( 42.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2022-11-28 16:22, Ard Biesheuvel wrote: > On Mon, 28 Nov 2022 at 17:17, Ryan Roberts > wrote: >> >> On 24/11/2022 12:39, Ard Biesheuvel wrote: >> > Add the required types and descriptor accessors to support 5 levels of >> > paging in the common code. This is one of the prerequisites for >> > supporting 52-bit virtual addressing with 4k pages. >> > >> > Note that this does not cover the code that handles kernel mappings or >> > the fixmap. >> > >> > Signed-off-by: Ard Biesheuvel >> > --- >> > arch/arm64/include/asm/pgalloc.h | 41 +++++++++++ >> > arch/arm64/include/asm/pgtable-hwdef.h | 22 +++++- >> > arch/arm64/include/asm/pgtable-types.h | 6 ++ >> > arch/arm64/include/asm/pgtable.h | 75 +++++++++++++++++++- >> > arch/arm64/mm/mmu.c | 31 +++++++- >> > arch/arm64/mm/pgd.c | 15 +++- >> > 6 files changed, 181 insertions(+), 9 deletions(-) >> > >> > diff --git a/arch/arm64/include/asm/pgalloc.h b/arch/arm64/include/asm/pgalloc.h >> > index 237224484d0f..cae8c648f462 100644 >> > --- a/arch/arm64/include/asm/pgalloc.h >> > +++ b/arch/arm64/include/asm/pgalloc.h >> > @@ -60,6 +60,47 @@ static inline void __p4d_populate(p4d_t *p4dp, phys_addr_t pudp, p4dval_t prot) >> > } >> > #endif /* CONFIG_PGTABLE_LEVELS > 3 */ >> > >> > +#if CONFIG_PGTABLE_LEVELS > 4 >> > + >> > +static inline void __pgd_populate(pgd_t *pgdp, phys_addr_t p4dp, pgdval_t prot) >> > +{ >> > + if (pgtable_l5_enabled()) >> > + set_pgd(pgdp, __pgd(__phys_to_pgd_val(p4dp) | prot)); >> > +} >> > + >> > +static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgdp, p4d_t *p4dp) >> > +{ >> > + pgdval_t pgdval = PGD_TYPE_TABLE; >> > + >> > + pgdval |= (mm == &init_mm) ? PGD_TABLE_UXN : PGD_TABLE_PXN; >> > + __pgd_populate(pgdp, __pa(p4dp), pgdval); >> > +} >> > + >> > +static inline p4d_t *p4d_alloc_one(struct mm_struct *mm, unsigned long addr) >> > +{ >> > + gfp_t gfp = GFP_PGTABLE_USER; >> > + >> > + if (mm == &init_mm) >> > + gfp = GFP_PGTABLE_KERNEL; >> > + return (p4d_t *)get_zeroed_page(gfp); >> > +} >> > + >> > +static inline void p4d_free(struct mm_struct *mm, p4d_t *p4d) >> > +{ >> > + if (!pgtable_l5_enabled()) >> > + return; >> > + BUG_ON((unsigned long)p4d & (PAGE_SIZE-1)); >> > + free_page((unsigned long)p4d); >> > +} >> > + >> > +#define __p4d_free_tlb(tlb, p4d, addr) p4d_free((tlb)->mm, p4d) >> > +#else >> > +static inline void __pgd_populate(pgd_t *pgdp, phys_addr_t p4dp, pgdval_t prot) >> > +{ >> > + BUILD_BUG(); >> > +} >> > +#endif /* CONFIG_PGTABLE_LEVELS > 4 */ >> > + >> > extern pgd_t *pgd_alloc(struct mm_struct *mm); >> > extern void pgd_free(struct mm_struct *mm, pgd_t *pgdp); >> > >> > diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h >> > index b91fe4781b06..b364b02e696b 100644 >> > --- a/arch/arm64/include/asm/pgtable-hwdef.h >> > +++ b/arch/arm64/include/asm/pgtable-hwdef.h >> > @@ -26,10 +26,10 @@ >> > #define ARM64_HW_PGTABLE_LEVELS(va_bits) (((va_bits) - 4) / (PAGE_SHIFT - 3)) >> > >> > /* >> > - * Size mapped by an entry at level n ( 0 <= n <= 3) >> > + * Size mapped by an entry at level n ( -1 <= n <= 3) >> > * We map (PAGE_SHIFT - 3) at all translation levels and PAGE_SHIFT bits >> > * in the final page. The maximum number of translation levels supported by >> > - * the architecture is 4. Hence, starting at level n, we have further >> > + * the architecture is 5. Hence, starting at level n, we have further >> > * ((4 - n) - 1) levels of translation excluding the offset within the page. >> > * So, the total number of bits mapped by an entry at level n is : >> > * >> >> Is it neccessary to represent the levels as (-1 - 3) in the kernel or >> are you >> open to switching to (0 - 4)? >> >> There are a couple of other places where translation level is used, >> which I >> found and fixed up for the KVM LPA2 support work. It got a bit messy >> to >> represent the levels using the architectural range (-1 - 3) so I ended >> up >> representing them as (0 - 4). The main issue was that KVM represents >> level as >> unsigned so that change would have looked quite big. >> >> Most of this is confined to KVM and the only place it really crosses >> over with >> the kernel is at __tlbi_level(). Which makes me think you might be >> missing some >> required changes (I didn't notice these in your other patches): >> >> Looking at the TLB management stuff, I think there are some places you >> will need >> to fix up to correctly handle the extra level in the kernel (e.g. >> tlb_get_level(), flush_tlb_range()). >> >> There are some new ecodings for level in the FSC field in the ESR. You >> might >> need to update the fault_info array in fault.c to represent these and >> correctly >> handle user space faults for the new level? >> > > Hi Ryan, > > Thanks for pointing this out. Once I have educated myself a bit more > about all of this, I should be able to answer your questions :-) > > I did not do any user space testing in anger on this series, on the > assumption that we already support 52-bit VAs, but I completely missed > the fact that the additional level of paging requires additional > attention. > > As for the level indexing: I have a slight preference for sticking > with the architectural range, but I don't deeply care either way. I'd really like to stick to the architectural representation, as there is an ingrained knowledge of the relation between a base granule size, a level, and a block mapping size. The nice thing about level '-1' is that it preserve this behaviour, and doesn't force everyone to adjust. It also makes it extremely easy to compare the code and the spec. So let's please stick to the [-1;3] range. It will save everyone a lot of trouble. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel