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Mon, 16 Mar 2020 13:14:24 +0000 MIME-Version: 1.0 Date: Mon, 16 Mar 2020 13:14:24 +0000 From: Marc Zyngier To: John Garry Subject: Re: [PATCH v3 2/2] irqchip/gic-v3-its: Balance initial LPI affinity across CPUs In-Reply-To: <2c367508-f81b-342e-eb05-8bbd1b056279@huawei.com> References: <20200316115433.9017-1-maz@kernel.org> <20200316115433.9017-3-maz@kernel.org> <2c367508-f81b-342e-eb05-8bbd1b056279@huawei.com> Message-ID: <9ce0b23455a06d92161c5302ac28152e@kernel.org> X-Sender: maz@kernel.org User-Agent: Roundcube Webmail/1.3.10 X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: john.garry@huawei.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, chenxiang66@hisilicon.com, wangzhou1@hisilicon.com, ming.lei@redhat.com, jason@lakedaemon.net, tglx@linutronix.de, luojiaxing@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200316_061426_948900_2A28BE7C X-CRM114-Status: GOOD ( 12.20 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Cooper , chenxiang , luojiaxing@huawei.com, linux-kernel@vger.kernel.org, Ming Lei , Zhou Wang , Thomas Gleixner , linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 2020-03-16 13:02, John Garry wrote: Hi John, > Hi Marc, > >> + int this_count = its_read_lpi_count(d, tmp); > > Not sure if it's intentional, but now there seems to be a subtle > difference to what Thomas described for non-managed interrupts - for > non-managed interrupts, x86 selects the CPU based on the total > interrupt load per CPU (or, more specifically, lowest vector > allocation count), and not just the non-managed load. Or maybe I > misread it. So far, I'm trying to keep the two allocation paths separate, as the two systems I have access to have very different behaviours: D05 has no managed interrupts to speak of, and my top-secret work machine has almost no unmanaged interrupts, so the two sets are almost completely disjoint. Also, it all depends on the interrupt allocation order, and whether something will rebalance the non-managed interrupts at a later time. At least, these two patches make it easy to alter the placement policy (the behaviour you describe above is a 2 line change). > Anyway, we can test this now for NVMe with its managed interrupts. Looking forward to hearing from you! M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel