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Fri, 05 May 2023 19:51:29 -0700 (PDT) Received: from [10.2.117.253] ([61.213.176.8]) by smtp.gmail.com with ESMTPSA id t23-20020a170902b21700b001aaefa0f82csm2442930plr.31.2023.05.05.19.51.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 05 May 2023 19:51:28 -0700 (PDT) Message-ID: <9d976db8-b800-ad84-9c67-0afb942934d9@bytedance.com> Date: Sat, 6 May 2023 10:51:23 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.10.1 Subject: Re: [QUESTION FOR ARM64 TLB] performance issue and implementation difference of TLB flush Content-Language: en-US To: Mark Rutland Cc: Will Deacon , Catalin Marinas , Ard Biesheuvel , Anshuman Khandual , Kefeng Wang , Feiyang Chen , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <2eb026b8-9e13-2b60-9e14-06417b142ac9@bytedance.com> <369d1be2-d418-1bfb-bfc2-b25e4e542d76@bytedance.com> From: Gang Li In-Reply-To: <369d1be2-d418-1bfb-bfc2-b25e4e542d76@bytedance.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230505_195134_876880_34F3B373 X-CRM114-Status: GOOD ( 12.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On 2023/4/28 17:27, Mark Rutland wrote:> The architecture allows a CPU to allocate TLB entries at any time for any > reason, for any valid translation table entries reachable from the > root in > TTBR{0,1}_ELx. That can be due to speculation, prefetching, and/or other > reasons. > TLB will be allocated due to prefetching or branch prediction. Will it be invalidated when the prediction fails? > Due to that, it doesn't matter whether or not a CPU explicitly accesses a > memory location -- TLB entries can be allocated regardless. > Consequently, the > spinlock doesn't make any difference. > And is there any kind of ARM manual or guide that explains these details to help us programming better? Thanks a lot for your help. Gang Li _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel