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Mon, 15 Sep 2025 10:35:23 -0700 (PDT) Received: from mars.fritz.box ([2a02:8071:7130:82c0:da34:bd1d:ae27:5be6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3e7c778f764sm13377778f8f.57.2025.09.15.10.35.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Sep 2025 10:35:22 -0700 (PDT) Message-ID: <9dd924871a81364a922131461339dec2a45d434e.camel@googlemail.com> Subject: [PATCH] drm/rockchip: rk3288-lvds: honor DCLK edge via GRF CON15 From: Christoph Fritz To: Heiko =?ISO-8859-1?Q?St=FCbner?= , Andy Yan Cc: Sandy Huang , linux-arm-kernel , linux-rockchip Date: Mon, 15 Sep 2025 19:35:22 +0200 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.46.4-2 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250915_103526_227183_5300F763 X-CRM114-Status: GOOD ( 14.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: chf.fritz@googlemail.com Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Set the DCLK edge (normal or invert) via GRF_SOC_CON15 when the specific drm_bus_flag is enabled. Keep track of the vop source in use so that the right DCLK (BIG: dclk0 or LIT: dclk1) gets set. This change is especially necessary for RGB output configurations to actually propagate the DCLK inversion. Signed-off-by: Christoph Fritz --- drivers/gpu/drm/rockchip/rockchip_lvds.c | 17 +++++++++++++++++ drivers/gpu/drm/rockchip/rockchip_lvds.h | 4 ++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/roc= kchip/rockchip_lvds.c index 2411260db51d7..08784c3ecf703 100644 --- a/drivers/gpu/drm/rockchip/rockchip_lvds.c +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c @@ -58,6 +58,7 @@ struct rockchip_lvds { struct drm_bridge *bridge; struct rockchip_encoder encoder; struct dev_pin_info *pins; + bool use_vop_lit; /* true if CON6 selects VOP_LIT */ }; =20 static inline struct rockchip_lvds *brige_to_lvds(struct drm_bridge *bridg= e) @@ -235,8 +236,11 @@ static int rk3288_lvds_grf_config(struct drm_encoder *= encoder, struct drm_display_mode *mode) { struct rockchip_lvds *lvds =3D encoder_to_lvds(encoder); + u32 bus_flgs =3D lvds->connector.display_info.bus_flags; + u8 con15_dclk =3D (bus_flgs & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0= ; u8 pin_hsync =3D (mode->flags & DRM_MODE_FLAG_PHSYNC) ? 1 : 0; u8 pin_dclk =3D (mode->flags & DRM_MODE_FLAG_PCSYNC) ? 1 : 0; + unsigned int con15_dclk_mask; u32 val; int ret; =20 @@ -260,6 +264,17 @@ static int rk3288_lvds_grf_config(struct drm_encoder *= encoder, if (ret) DRM_DEV_ERROR(lvds->dev, "Could not write to GRF: %d\n", ret); =20 + /* SOC_CON15 DCLK normal/invert */ + con15_dclk_mask =3D lvds->use_vop_lit ? + RK3288_LVDS_SOC_CON15_LIT_DCLK1_INVERT : + RK3288_LVDS_SOC_CON15_BIG_DCLK0_INVERT; + + val =3D con15_dclk ? con15_dclk_mask : 0; + val |=3D con15_dclk_mask << 16; + ret =3D regmap_write(lvds->grf, RK3288_LVDS_GRF_SOC_CON15, val); + if (ret) + DRM_DEV_ERROR(lvds->dev, "Could not write to CON15: %d\n", ret); + return ret; } =20 @@ -273,6 +288,8 @@ static int rk3288_lvds_set_vop_source(struct rockchip_l= vds *lvds, if (ret < 0) return ret; =20 + lvds->use_vop_lit =3D !!ret; + val =3D RK3288_LVDS_SOC_CON6_SEL_VOP_LIT << 16; if (ret) val |=3D RK3288_LVDS_SOC_CON6_SEL_VOP_LIT; diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.h b/drivers/gpu/drm/roc= kchip/rockchip_lvds.h index 2d92447d819be..81081b84eea6a 100644 --- a/drivers/gpu/drm/rockchip/rockchip_lvds.h +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.h @@ -77,6 +77,10 @@ =20 #define RK3288_LVDS_GRF_SOC_CON6 0x025C #define RK3288_LVDS_GRF_SOC_CON7 0x0260 +#define RK3288_LVDS_GRF_SOC_CON15 0x03a4 + +#define RK3288_LVDS_SOC_CON15_BIG_DCLK0_INVERT BIT(13) +#define RK3288_LVDS_SOC_CON15_LIT_DCLK1_INVERT BIT(15) =20 /* fbdiv value is split over 2 registers, with bit8 in reg2 */ #define RK3288_LVDS_PLL_FBDIV_REG2(_fbd) \ --=20 2.39.5