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Fri, 5 Sep 2025 00:18:56 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Fri, 5 Sep 2025 00:18:56 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Fri, 5 Sep 2025 00:18:55 -0500 Received: from [10.24.68.177] (akashdeep-hp-z2-tower-g5-workstation.dhcp.ti.com [10.24.68.177]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5855IpZV4124087; Fri, 5 Sep 2025 00:18:52 -0500 Message-ID: <9e0c355c-8b19-438e-98d9-d6290a562863@ti.com> Date: Fri, 5 Sep 2025 10:48:51 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/3] arm64: dts: ti: k3-pinctrl: Add the remaining macros To: "Kumar, Udit" , , , , , , , , , , , , CC: , References: <20250902071917.1616729-1-a-kaur@ti.com> <20250902071917.1616729-4-a-kaur@ti.com> <1a20e784-d2d7-46d7-b705-67e460b6ae33@ti.com> <8f0dc883-7bab-4ad8-8db2-6c8f8377fdb3@ti.com> Content-Language: en-US From: Akashdeep Kaur In-Reply-To: <8f0dc883-7bab-4ad8-8db2-6c8f8377fdb3@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250904_221859_640659_B510691A X-CRM114-Status: GOOD ( 10.08 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 05/09/25 10:27, Kumar, Udit wrote: > > On 9/4/2025 7:16 PM, Akashdeep Kaur wrote: >> Hi Udit, >> >> On 04/09/25 18:06, Kumar, Udit wrote: >>> >> >> ... >> >>>> ... >>>>>>   #define PULLTYPESEL_SHIFT    (17) >>>>>>   #define RXACTIVE_SHIFT        (18) >>>>>> +#define DRV_STR_SHIFT           (19) >>>>> >>>>> referring to above TRM mentioned in commit message >>>>> >>>>> Bit 20-19 are for DRV_STR, and description says >>>>> >>>>> 0 - Default >>>>> 1 - Reserved >>>>> 2 - Reserved >>>>> 3 - Reserved >>>>> >>>>> Not sure, is there some additional document to be referred for >>>>> PIN_DRIVE_STRENGTH >>>> >>>> This information will be updated in TRM in coming cycles. >>> >>> >>> Sorry , >>> >>> can not ack before TRM update >> >> The information can be found at https://www.ti.com/lit/ug/spruj83b/ >> spruj83b.pdf in Table 14-8769. Description Of The Pad Configuration >> Register Bit > > > Then please give correct reference in commit message Updated the commit message! > > > >> >>> >>> >>> >>>>> >>>>> >>>>>> +#define DS_ISO_OVERRIDE_SHIFT (22) >>>>>> +#define DS_ISO_BYPASS_EN_SHIFT  (23) >>>>> >> >> ... >> >>>>> >>>>>>   /* Default mux configuration for gpio-ranges to use with pinctrl */ >>>>>>   #define PIN_GPIO_RANGE_IOPAD    (PIN_INPUT | 7) >>>> >>>> Regards, >>>> Akashdeep Kaur >> >> Thanks, >> Akashdeep Kaur >>