From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, NICE_REPLY_A,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 55213C433E7 for ; Fri, 16 Oct 2020 13:17:47 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D4FFC206E5 for ; Fri, 16 Oct 2020 13:17:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="WyvcDE+g" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D4FFC206E5 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=fNUssMMVkiGHGm75q/WUYC98A4w33Pn43f3DtAbi1GY=; b=WyvcDE+gptzcYHM771lAJku7L Mikn/hQSU7h4ey138EWWrAVtOANg2DrrDX4MF786BBf7IPjNT4K2abR7IsCHjkzENc4gogmXjWe6d oh9lR2UWjWQx+D0vIvYTBXpr/Is0xCObZ13c8zn245BnJaTw6gMcGMno+WAZ2GK7wAM76vmSgxTzD Bu1yQTEMTk1qx2PQaafQeUazBKfD9I6Q/ge5oE16U0JHn6nxfiyGP73f7Q3yaRolHH/8YiDKLqJEE QVoykJhGadwhM+3WKjhJsCXbYO7ImEXD/yLjn5LTi4Jw+d9h5LapHgINlr4vPIgqOCk0w8deDjrrB FUMkE6Z2A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kTPaY-0004vy-Ew; Fri, 16 Oct 2020 13:16:06 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kTPaV-0004ui-JM for linux-arm-kernel@lists.infradead.org; Fri, 16 Oct 2020 13:16:04 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5260C1FB; Fri, 16 Oct 2020 06:16:02 -0700 (PDT) Received: from [10.57.50.28] (unknown [10.57.50.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6C61E3F71F; Fri, 16 Oct 2020 06:16:00 -0700 (PDT) Subject: Re: [PATCH] coresight: etm4x: Skip setting LPOVERRIDE bit for qcom,skip-power-up To: Sai Prakash Ranjan References: <20201016101025.26505-1-saiprakash.ranjan@codeaurora.org> <5c4f6f5d-b07d-0816-331f-7c7463fa99b3@arm.com> <41bbcd43c2b016b6d785c3750622e9fe@codeaurora.org> From: Suzuki Poulose Message-ID: <9e19d312-9de4-2ed8-75ca-c774b93bfe11@arm.com> Date: Fri, 16 Oct 2020 14:15:58 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.3.1 MIME-Version: 1.0 In-Reply-To: <41bbcd43c2b016b6d785c3750622e9fe@codeaurora.org> Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201016_091603_754023_0C35CB5C X-CRM114-Status: GOOD ( 19.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: denik@chromium.org, Mathieu Poirier , linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org, Stephen Boyd , linux-arm-kernel@lists.infradead.org, Mike Leach Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10/16/20 12:47 PM, Sai Prakash Ranjan wrote: > Hi Suzuki, > > On 2020-10-16 16:51, Suzuki Poulose wrote: >> Hi Sai, >> >> On 10/16/20 11:10 AM, Sai Prakash Ranjan wrote: >>> There is a bug on the systems supporting to skip power up >>> (qcom,skip-power-up) where setting LPOVERRIDE bit(low-power >>> state override behaviour) will result in CPU hangs/lockups >>> even on the implementations which supports it. So skip >>> setting the LPOVERRIDE bit for such platforms. >>> >>> Fixes: 02510a5aa78d ("coresight: etm4x: Add support to skip trace >>> unit power up") >>> Signed-off-by: Sai Prakash Ranjan >> >> The fix is fine by me. Btw, is there a hardware Erratum assigned for >> this ? It would be good to have the Erratum documented somewhere, >> preferrably ( Documentation/arm64/silicon-errata.rst ) >> > > No, afaik we don't have any erratum assigned to this bug. Ok. Please double check, if there are any. > It was already present in downstream kernel and since we > support these targets with the previous HW bug > (qcom,skip-power-up) now in upstream, we would need this > fix in upstream kernel as well. I understand the need for the fix and we must fix it. I was looking to document this in the central place for errata's handled in the kernel. And I missed asking this question when the original patch was posted. So, thought of asking the question now anyways. Better late than never ;-) Reviewed-by: Suzuki K Poulose _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel