From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABE95C433E2 for ; Tue, 14 Jul 2020 09:12:26 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 71C4421D7B for ; Tue, 14 Jul 2020 09:12:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="AJv7zJR4" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 71C4421D7B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=socionext.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=I+00GnoNLjQYYDOpbknl7zWwMyVZkBEaV5aprfFrqRo=; b=AJv7zJR4zCXZujUCivkuvXw3E BucTmGVHkJKwq9SsrsQ4Cjb1sOhKcgd2oM4659VsIArxquhei3acFcBgb2v29idIMVTkV3camF7Iv QWaTGqa/GD3ktLHngNNK7h2JO++Iq3vdSlmXEcg8eMEugWTKxiOggZ3wylCn6zCJTA9rqktl3zKgf LYhZObJXKffaL/p1KLhrL5BR6Tcs0JAWTrYKLySANdwp5mQkZeGA71lJzwHQRkKq087ckNvqF3m5x sLwCti0XYjCecwtzCkSAgW33HaYIo4QmkBgiH0Xi+V4SNh35Kc15ZFrX8lx/Rb+lDjMC7a4HHhBgQ 7MtMN/Gvg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jvGxn-0004ba-7s; Tue, 14 Jul 2020 09:10:59 +0000 Received: from mx.socionext.com ([202.248.49.38]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1jvGxj-0004ZX-9d for linux-arm-kernel@lists.infradead.org; Tue, 14 Jul 2020 09:10:56 +0000 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 14 Jul 2020 18:10:51 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 9ACA460060; Tue, 14 Jul 2020 18:10:51 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Tue, 14 Jul 2020 18:10:51 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id 2AC731A0508; Tue, 14 Jul 2020 18:10:51 +0900 (JST) Received: from [10.212.0.26] (unknown [10.212.0.26]) by yuzu.css.socionext.com (Postfix) with ESMTP id C7F8F12012F; Tue, 14 Jul 2020 18:10:50 +0900 (JST) Subject: Re: [PATCH v2 2/2] phy: socionext: Add UniPhier AHCI PHY driver support To: Vinod Koul References: <1593507574-10007-1-git-send-email-hayashi.kunihiko@socionext.com> <1593507574-10007-3-git-send-email-hayashi.kunihiko@socionext.com> <20200713050527.GR34333@vkoul-mobl> From: Kunihiko Hayashi Message-ID: <9f358850-eb2a-769c-be57-866d77183a7f@socionext.com> Date: Tue, 14 Jul 2020 18:10:50 +0900 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200713050527.GR34333@vkoul-mobl> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200714_051055_654908_A84FA71A X-CRM114-Status: GOOD ( 20.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kishon Vijay Abraham I , Masahiro Yamada , Rob Herring , linux-arm-kernel@lists.infradead.org Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Vinod, On 2020/07/13 14:05, Vinod Koul wrote: > On 30-06-20, 17:59, Kunihiko Hayashi wrote: > >> +++ b/drivers/phy/socionext/phy-uniphier-ahci.c >> @@ -0,0 +1,335 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * phy-uniphier-ahci.c - PHY driver for UniPhier AHCI controller >> + * Copyright 2016-2018, Socionext Inc. > > we are in 2020 now! Oops, I'll adjust it. >> +static int uniphier_ahciphy_pxs2_power_on(struct uniphier_ahciphy_priv *priv) >> +{ >> + int ret; >> + u32 val; >> + >> + /* enable reference clock for PHY */ >> + val = readl(priv->base + CKCTRL); >> + val |= CKCTRL_REF_SSP_EN; >> + writel(val, priv->base + CKCTRL); >> + >> + /* release port reset */ >> + val = readl(priv->base + CKCTRL); >> + val &= ~CKCTRL_P0_RESET; >> + writel(val, priv->base + CKCTRL); >> + >> + /* wait until PLL is ready */ >> + if (priv->data->is_ready_high) >> + ret = readl_poll_timeout(priv->base + CKCTRL, val, >> + (val & CKCTRL_P0_READY), 200, 400); >> + else >> + ret = readl_poll_timeout(priv->base + CKCTRL, val, >> + !(val & CKCTRL_P0_READY), 200, 400); >> + if (ret) { >> + dev_err(priv->dev, "Failed to check whether PHY PLL is ready\n"); >> + goto out_disable_clock; >> + } >> + >> + return 0; >> + >> +out_disable_clock: >> + /* assert port reset */ >> + val = readl(priv->base + CKCTRL); >> + val |= CKCTRL_P0_RESET; >> + writel(val, priv->base + CKCTRL); >> + >> + /* disable reference clock for PHY */ >> + val = readl(priv->base + CKCTRL); >> + val &= ~CKCTRL_REF_SSP_EN; >> + writel(val, priv->base + CKCTRL); > > this seems to be repeated patter, why not add a modifyl() helper here.. Hmm, I try to add helpers for modifying P0_RESET and REF_SSP_EN bits. > >> +static int uniphier_ahciphy_pxs3_init(struct uniphier_ahciphy_priv *priv) >> +{ >> + int i; >> + u32 val; >> + >> + /* setup port parameter */ >> + val = readl(priv->base + TXCTRL0); >> + val &= ~TXCTRL0_AMP_G3_MASK; >> + val |= FIELD_PREP(TXCTRL0_AMP_G3_MASK, 0x73); >> + val &= ~TXCTRL0_AMP_G2_MASK; >> + val |= FIELD_PREP(TXCTRL0_AMP_G2_MASK, 0x46); >> + val &= ~TXCTRL0_AMP_G1_MASK; >> + val |= FIELD_PREP(TXCTRL0_AMP_G1_MASK, 0x42); >> + writel(val, priv->base + TXCTRL0); >> + >> + val = readl(priv->base + TXCTRL1); >> + val &= ~TXCTRL1_DEEMPH_G3_MASK; >> + val |= FIELD_PREP(TXCTRL1_DEEMPH_G3_MASK, 0x23); >> + val &= ~TXCTRL1_DEEMPH_G2_MASK; >> + val |= FIELD_PREP(TXCTRL1_DEEMPH_G2_MASK, 0x05); >> + val &= ~TXCTRL1_DEEMPH_G1_MASK; >> + val |= FIELD_PREP(TXCTRL1_DEEMPH_G1_MASK, 0x05); >> + >> + val = readl(priv->base + RXCTRL); >> + val &= ~RXCTRL_LOS_LVL_MASK; >> + val |= FIELD_PREP(RXCTRL_LOS_LVL_MASK, 0x9); >> + val &= ~RXCTRL_LOS_BIAS_MASK; >> + val |= FIELD_PREP(RXCTRL_LOS_BIAS_MASK, 0x2); >> + val &= ~RXCTRL_RX_EQ_MASK; >> + val |= FIELD_PREP(RXCTRL_RX_EQ_MASK, 0x1); >> + >> + /* dummy read 25 times */ > > why? According to the specification document, these 25 read accesses make a wait time for the phy to stablize. I'll add the reason as comment. > >> +static int uniphier_ahciphy_init(struct phy *phy) >> +{ >> + struct uniphier_ahciphy_priv *priv = phy_get_drvdata(phy); >> + int ret; >> + >> + ret = clk_prepare_enable(priv->clk_parent); >> + if (ret) >> + return ret; >> + >> + ret = reset_control_deassert(priv->rst_parent); >> + if (ret) >> + goto out_clk_disable; >> + >> + if (priv->data->init) { >> + ret = priv->data->init(priv); >> + if (ret) >> + goto out_rst_assert; >> + } >> + >> + return ret; > > return 0? Yes, I'll fix it. > >> +static const struct uniphier_ahciphy_soc_data uniphier_pxs2_data = { >> + .init = NULL, > > Isn't this superfluous ? Indeed, this can be removed. Thank you, --- Best Regards Kunihiko Hayashi _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel