From: Marek Vasut <marek.vasut@mailbox.org>
To: Geert Uytterhoeven <geert@linux-m68k.org>,
Marek Vasut <marek.vasut+renesas@mailbox.org>
Cc: linux-pci@vger.kernel.org,
"Yoshihiro Shimoda" <yoshihiro.shimoda.uh@renesas.com>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Catalin Marinas" <catalin.marinas@arm.com>,
"Conor Dooley" <conor+dt@kernel.org>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Marc Zyngier" <maz@kernel.org>, "Rob Herring" <robh@kernel.org>,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH 1/3] PCI: rcar-gen4: Configure AXIINTC if iMSI-RX not used
Date: Thu, 18 Jun 2026 04:21:54 +0200 [thread overview]
Message-ID: <9fb93f5f-51dc-47aa-aa8e-53cceaef876e@mailbox.org> (raw)
In-Reply-To: <CAMuHMdU0SJ0q2hcpu+qZCH3eZ5eFDyo8Z964h9DhuSaQ7QdHSg@mail.gmail.com>
On 6/17/26 10:26 AM, Geert Uytterhoeven wrote:
Hello Geert,
>> +static void rcar_gen4_pcie_host_msi_init(struct dw_pcie_rp *pp)
>> +{
>> + struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
>> + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
>> + u32 val;
>> +
>> + /* Make sure MSICAP0 MSIE is configured. */
>> + val = dw_pcie_readl_dbi(dw, MSICAP0);
>> + if (pci_msi_enabled())
>> + val |= MSICAP0_MSIE;
>> + else
>> + val &= ~MSICAP0_MSIE;
>> + dw_pcie_writel_dbi(dw, MSICAP0, val);
>> +
>> + if (!pci_msi_enabled() || pp->use_imsi_rx) {
>> + /* Clear AXIINTC mapping. */
>> + writel(0, rcar->base + AXIINTCADDR);
>> + writel(0, rcar->base + AXIINTCCONT);
>> + } else {
>> + /* Point AXIINTC to GIC ITS and enable. */
>> + writel(AXIINTCADDR_VAL, rcar->base + AXIINTCADDR);
>> + writel(INTC_EN | INTC_MASK, rcar->base + AXIINTCCONT);
>> + }
>> +
>> + /* Configure MSI interrupt signal */
>> + val = readl(rcar->base + PCIEINTSTS0EN);
>> + if (pci_msi_enabled())
>> + val |= MSI_CTRL_INT;
>> + else
>> + val &= ~MSI_CTRL_INT;
>> + writel(val, rcar->base + PCIEINTSTS0EN);
>> +}
>> +
>> static int rcar_gen4_pcie_enable_device(struct pci_host_bridge *bridge,
>
> FTR, this has a contextual dependency on "[PATCH v2] PCI: rcar-gen4:
> Limit Max_Read_Request_Size and Max_Payload_Size to 256 Bytes"
> (https://lore.kernel.org/all/20260519195219.189323-1-marek.vasut+renesas@mailbox.org).
It is not an explicit dependency, I only had these patches in my tree
and clearly that was an interaction. I'll rebase this dependency out for V2.
Thanks!
--
Best regards,
Marek Vasut
next prev parent reply other threads:[~2026-06-18 2:54 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-17 2:59 [PATCH 1/3] PCI: rcar-gen4: Configure AXIINTC if iMSI-RX not used Marek Vasut
2026-06-17 2:59 ` [PATCH 2/3] irqchip/gic-v3: Add Renesas R-Car Gen4 erratum workaround Marek Vasut
2026-06-17 7:09 ` Geert Uytterhoeven
2026-06-18 2:38 ` Marek Vasut
2026-06-17 7:24 ` Marc Zyngier
2026-06-18 2:50 ` Marek Vasut
2026-06-18 8:38 ` Marc Zyngier
2026-06-17 2:59 ` [PATCH 3/3] arm64: dts: renesas: r8a779g0: Add GICv3 ITS and update PCIe nodes Marek Vasut
2026-06-17 7:28 ` [PATCH 1/3] PCI: rcar-gen4: Configure AXIINTC if iMSI-RX not used Marc Zyngier
2026-06-17 8:26 ` Geert Uytterhoeven
2026-06-18 2:21 ` Marek Vasut [this message]
2026-06-17 10:33 ` Manivannan Sadhasivam
2026-06-18 3:21 ` Marek Vasut
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