[PATCH 02/35] Documentation: arm: correct spelling

[PATCH 02/35] Documentation: arm: correct spelling

[Randy Dunlap]

Correct spelling problems for Documentation/arm/ as reported
by codespell.

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Russell King <linux@armlinux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: linux-doc@vger.kernel.org
---
 Documentation/arm/arm.rst                           |    2 +-
 Documentation/arm/ixp4xx.rst                        |    4 ++--
 Documentation/arm/keystone/knav-qmss.rst            |    2 +-
 Documentation/arm/stm32/stm32-dma-mdma-chaining.rst |    6 +++---
 Documentation/arm/sunxi/clocks.rst                  |    2 +-
 Documentation/arm/swp_emulation.rst                 |    2 +-
 Documentation/arm/tcm.rst                           |    2 +-
 Documentation/arm/vlocks.rst                        |    2 +-
 8 files changed, 11 insertions(+), 11 deletions(-)

diff -- a/Documentation/arm/ixp4xx.rst b/Documentation/arm/ixp4xx.rst
--- a/Documentation/arm/ixp4xx.rst
+++ b/Documentation/arm/ixp4xx.rst
@@ -78,9 +78,9 @@ IXP4xx provides two methods of accessing
 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
    To access PCI via this space, we simply ioremap() the BAR
    into the kernel and we can use the standard read[bwl]/write[bwl]
-   macros. This is the preffered method due to speed but it
+   macros. This is the preferred method due to speed but it
    limits the system to just 64MB of PCI memory. This can be
-   problamatic if using video cards and other memory-heavy devices.
+   problematic if using video cards and other memory-heavy devices.
 
 2) If > 64MB of memory space is required, the IXP4xx can be
    configured to use indirect registers to access PCI This allows
diff -- a/Documentation/arm/swp_emulation.rst b/Documentation/arm/swp_emulation.rst
--- a/Documentation/arm/swp_emulation.rst
+++ b/Documentation/arm/swp_emulation.rst
@@ -1,7 +1,7 @@
 Software emulation of deprecated SWP instruction (CONFIG_SWP_EMULATE)
 ---------------------------------------------------------------------
 
-ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommeds
+ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommends
 moving to the load-locked/store-conditional instructions LDREX and STREX.
 
 ARMv7 multiprocessing extensions introduce the ability to disable these
diff -- a/Documentation/arm/tcm.rst b/Documentation/arm/tcm.rst
--- a/Documentation/arm/tcm.rst
+++ b/Documentation/arm/tcm.rst
@@ -71,7 +71,7 @@ in <asm/tcm.h>. Using this interface it
 
 - Have the remaining TCM RAM added to a special
   allocation pool with gen_pool_create() and gen_pool_add()
-  and provice tcm_alloc() and tcm_free() for this
+  and provide tcm_alloc() and tcm_free() for this
   memory. Such a heap is great for things like saving
   device state when shutting off device power domains.
 
diff -- a/Documentation/arm/stm32/stm32-dma-mdma-chaining.rst b/Documentation/arm/stm32/stm32-dma-mdma-chaining.rst
--- a/Documentation/arm/stm32/stm32-dma-mdma-chaining.rst
+++ b/Documentation/arm/stm32/stm32-dma-mdma-chaining.rst
@@ -359,7 +359,7 @@ Driver updates for STM32 DMA-MDMA chaini
     descriptor you want a callback to be called at the end of the transfer
     (dmaengine_prep_slave_sg()) or the period (dmaengine_prep_dma_cyclic()).
     Depending on the direction, set the callback on the descriptor that finishes
-    the overal transfer:
+    the overall transfer:
 
     * DMA_DEV_TO_MEM: set the callback on the "MDMA" descriptor
     * DMA_MEM_TO_DEV: set the callback on the "DMA" descriptor
@@ -371,7 +371,7 @@ Driver updates for STM32 DMA-MDMA chaini
   As STM32 MDMA channel transfer is triggered by STM32 DMA, you must issue
   STM32 MDMA channel before STM32 DMA channel.
 
-  If any, your callback will be called to warn you about the end of the overal
+  If any, your callback will be called to warn you about the end of the overall
   transfer or the period completion.
 
   Don't forget to terminate both channels. STM32 DMA channel is configured in
@@ -412,4 +412,4 @@ Resources
 
 :Authors:
 
-- Amelie Delaunay <amelie.delaunay@foss.st.com>
\ No newline at end of file
+- Amelie Delaunay <amelie.delaunay@foss.st.com>
diff -- a/Documentation/arm/arm.rst b/Documentation/arm/arm.rst
--- a/Documentation/arm/arm.rst
+++ b/Documentation/arm/arm.rst
@@ -141,7 +141,7 @@ ST506 hard drives
   `*configure` harddrive set to 2). I've got an internal 20MB and a great
   big external 5.25" FH 64MB drive (who could ever want more :-) ).
 
-  I've just got 240K/s off it (a dd with bs=128k); thats about half of what
+  I've just got 240K/s off it (a dd with bs=128k); that's about half of what
   RiscOS gets; but it's a heck of a lot better than the 50K/s I was getting
   last week :-)
 
diff -- a/Documentation/arm/keystone/knav-qmss.rst b/Documentation/arm/keystone/knav-qmss.rst
--- a/Documentation/arm/keystone/knav-qmss.rst
+++ b/Documentation/arm/keystone/knav-qmss.rst
@@ -39,7 +39,7 @@ CPPI/QMSS Low Level Driver document (doc
 
 	git://git.ti.com/keystone-rtos/qmss-lld.git
 
-k2_qmss_pdsp_acc48_k2_le_1_0_0_9.bin firmware supports upto 48 accumulator
+k2_qmss_pdsp_acc48_k2_le_1_0_0_9.bin firmware supports up to 48 accumulator
 channels. This firmware is available under ti-keystone folder of
 firmware.git at
 
diff -- a/Documentation/arm/sunxi/clocks.rst b/Documentation/arm/sunxi/clocks.rst
--- a/Documentation/arm/sunxi/clocks.rst
+++ b/Documentation/arm/sunxi/clocks.rst
@@ -5,7 +5,7 @@ Frequently asked questions about the sun
 This document contains useful bits of information that people tend to ask
 about the sunxi clock system, as well as accompanying ASCII art when adequate.
 
-Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the
+Q: Why is the main 24MHz oscillator gateable? Wouldn't that break the
    system?
 
 A: The 24MHz oscillator allows gating to save power. Indeed, if gated
diff -- a/Documentation/arm/vlocks.rst b/Documentation/arm/vlocks.rst
--- a/Documentation/arm/vlocks.rst
+++ b/Documentation/arm/vlocks.rst
@@ -155,7 +155,7 @@ the basic algorithm:
    optimisation.
 
    If there are too many CPUs to read the currently_voting array in
-   one transaction then multiple transations are still required.  The
+   one transaction then multiple transactions are still required.  The
    implementation uses a simple loop of word-sized loads for this
    case.  The number of transactions is still fewer than would be
    required if bytes were loaded individually.

_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH 02/35] Documentation: arm: correct spelling

[Mukesh Ojha]

Hi,

Thanks for the patch.

On 1/27/2023 12:09 PM, Randy Dunlap wrote:
> Correct spelling problems for Documentation/arm/ as reported
> by codespell.
> 
> Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: Jonathan Corbet <corbet@lwn.net>
> Cc: linux-doc@vger.kernel.org
> ---
>   Documentation/arm/arm.rst                           |    2 +-
>   Documentation/arm/ixp4xx.rst                        |    4 ++--
>   Documentation/arm/keystone/knav-qmss.rst            |    2 +-
>   Documentation/arm/stm32/stm32-dma-mdma-chaining.rst |    6 +++---
>   Documentation/arm/sunxi/clocks.rst                  |    2 +-
>   Documentation/arm/swp_emulation.rst                 |    2 +-
>   Documentation/arm/tcm.rst                           |    2 +-
>   Documentation/arm/vlocks.rst                        |    2 +-
>   8 files changed, 11 insertions(+), 11 deletions(-)
> 
> diff -- a/Documentation/arm/ixp4xx.rst b/Documentation/arm/ixp4xx.rst
> --- a/Documentation/arm/ixp4xx.rst
> +++ b/Documentation/arm/ixp4xx.rst
> @@ -78,9 +78,9 @@ IXP4xx provides two methods of accessing
>   1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
>      To access PCI via this space, we simply ioremap() the BAR
>      into the kernel and we can use the standard read[bwl]/write[bwl]
> -   macros. This is the preffered method due to speed but it
> +   macros. This is the preferred method due to speed but it
>      limits the system to just 64MB of PCI memory. This can be
> -   problamatic if using video cards and other memory-heavy devices.
> +   problematic if using video cards and other memory-heavy devices.
>   
>   2) If > 64MB of memory space is required, the IXP4xx can be
>      configured to use indirect registers to access PCI This allows
> diff -- a/Documentation/arm/swp_emulation.rst b/Documentation/arm/swp_emulation.rst
> --- a/Documentation/arm/swp_emulation.rst
> +++ b/Documentation/arm/swp_emulation.rst
> @@ -1,7 +1,7 @@
>   Software emulation of deprecated SWP instruction (CONFIG_SWP_EMULATE)
>   ---------------------------------------------------------------------
>   
> -ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommeds
> +ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommends
>   moving to the load-locked/store-conditional instructions LDREX and STREX.
>   
>   ARMv7 multiprocessing extensions introduce the ability to disable these
> diff -- a/Documentation/arm/tcm.rst b/Documentation/arm/tcm.rst
> --- a/Documentation/arm/tcm.rst
> +++ b/Documentation/arm/tcm.rst
> @@ -71,7 +71,7 @@ in <asm/tcm.h>. Using this interface it
>   
>   - Have the remaining TCM RAM added to a special
>     allocation pool with gen_pool_create() and gen_pool_add()
> -  and provice tcm_alloc() and tcm_free() for this
> +  and provide tcm_alloc() and tcm_free() for this
>     memory. Such a heap is great for things like saving
>     device state when shutting off device power domains.
>   
> diff -- a/Documentation/arm/stm32/stm32-dma-mdma-chaining.rst b/Documentation/arm/stm32/stm32-dma-mdma-chaining.rst
> --- a/Documentation/arm/stm32/stm32-dma-mdma-chaining.rst
> +++ b/Documentation/arm/stm32/stm32-dma-mdma-chaining.rst
> @@ -359,7 +359,7 @@ Driver updates for STM32 DMA-MDMA chaini
>       descriptor you want a callback to be called at the end of the transfer
>       (dmaengine_prep_slave_sg()) or the period (dmaengine_prep_dma_cyclic()).
>       Depending on the direction, set the callback on the descriptor that finishes
> -    the overal transfer:
> +    the overall transfer:
>   
>       * DMA_DEV_TO_MEM: set the callback on the "MDMA" descriptor
>       * DMA_MEM_TO_DEV: set the callback on the "DMA" descriptor
> @@ -371,7 +371,7 @@ Driver updates for STM32 DMA-MDMA chaini
>     As STM32 MDMA channel transfer is triggered by STM32 DMA, you must issue
>     STM32 MDMA channel before STM32 DMA channel.
>   
> -  If any, your callback will be called to warn you about the end of the overal
> +  If any, your callback will be called to warn you about the end of the overall
>     transfer or the period completion.
>   
>     Don't forget to terminate both channels. STM32 DMA channel is configured in
> @@ -412,4 +412,4 @@ Resources
>   
>   :Authors:
>   
> -- Amelie Delaunay <amelie.delaunay@foss.st.com>
> \ No newline at end of file
> +- Amelie Delaunay <amelie.delaunay@foss.st.com>
> diff -- a/Documentation/arm/arm.rst b/Documentation/arm/arm.rst
> --- a/Documentation/arm/arm.rst
> +++ b/Documentation/arm/arm.rst
> @@ -141,7 +141,7 @@ ST506 hard drives
>     `*configure` harddrive set to 2). I've got an internal 20MB and a great
>     big external 5.25" FH 64MB drive (who could ever want more :-) ).
>   
> -  I've just got 240K/s off it (a dd with bs=128k); thats about half of what
> +  I've just got 240K/s off it (a dd with bs=128k); that's about half of what
>     RiscOS gets; but it's a heck of a lot better than the 50K/s I was getting
>     last week :-)
>   
> diff -- a/Documentation/arm/keystone/knav-qmss.rst b/Documentation/arm/keystone/knav-qmss.rst
> --- a/Documentation/arm/keystone/knav-qmss.rst
> +++ b/Documentation/arm/keystone/knav-qmss.rst
> @@ -39,7 +39,7 @@ CPPI/QMSS Low Level Driver document (doc
>   
>   	git://git.ti.com/keystone-rtos/qmss-lld.git
>   
> -k2_qmss_pdsp_acc48_k2_le_1_0_0_9.bin firmware supports upto 48 accumulator
> +k2_qmss_pdsp_acc48_k2_le_1_0_0_9.bin firmware supports up to 48 accumulator
>   channels. This firmware is available under ti-keystone folder of
>   firmware.git at
>   
> diff -- a/Documentation/arm/sunxi/clocks.rst b/Documentation/arm/sunxi/clocks.rst
> --- a/Documentation/arm/sunxi/clocks.rst
> +++ b/Documentation/arm/sunxi/clocks.rst
> @@ -5,7 +5,7 @@ Frequently asked questions about the sun
>   This document contains useful bits of information that people tend to ask
>   about the sunxi clock system, as well as accompanying ASCII art when adequate.
>   
> -Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the
> +Q: Why is the main 24MHz oscillator gateable? Wouldn't that break the
>      system?
>   
>   A: The 24MHz oscillator allows gating to save power. Indeed, if gated
> diff -- a/Documentation/arm/vlocks.rst b/Documentation/arm/vlocks.rst
> --- a/Documentation/arm/vlocks.rst
> +++ b/Documentation/arm/vlocks.rst
> @@ -155,7 +155,7 @@ the basic algorithm:
>      optimisation.
>   
>      If there are too many CPUs to read the currently_voting array in
> -   one transaction then multiple transations are still required.  The
> +   one transaction then multiple transactions are still required.  The
>      implementation uses a simple loop of word-sized loads for this
>      case.  The number of transactions is still fewer than would be
>      required if bytes were loaded individually.
> 

Reviewed-by: Mukesh Ojha <quic_mojha@quicinc.com>

-Mukesh

> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

_______________________________________________
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[PATCH 01/35] Documentation: arm64: correct spelling

[Randy Dunlap]

Correct spelling problems for Documentation/arm64/ as reported
by codespell.

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: linux-doc@vger.kernel.org
---
 Documentation/arm64/booting.rst    |    2 +-
 Documentation/arm64/elf_hwcaps.rst |    2 +-
 Documentation/arm64/sve.rst        |    4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff -- a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
--- a/Documentation/arm64/booting.rst
+++ b/Documentation/arm64/booting.rst
@@ -223,7 +223,7 @@ Before jumping into the kernel, the foll
   For systems with a GICv3 interrupt controller to be used in v3 mode:
   - If EL3 is present:
 
-      - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
+      - ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1.
       - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
       - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
         all CPUs the kernel is executing on, and must stay constant
diff -- a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst
--- a/Documentation/arm64/elf_hwcaps.rst
+++ b/Documentation/arm64/elf_hwcaps.rst
@@ -14,7 +14,7 @@ Some hardware or software features are o
 implementations, and/or with certain kernel configurations, but have no
 architected discovery mechanism available to userspace code at EL0. The
 kernel exposes the presence of these features to userspace through a set
-of flags called hwcaps, exposed in the auxilliary vector.
+of flags called hwcaps, exposed in the auxiliary vector.
 
 Userspace software can test for features by acquiring the AT_HWCAP or
 AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant
diff -- a/Documentation/arm64/sve.rst b/Documentation/arm64/sve.rst
--- a/Documentation/arm64/sve.rst
+++ b/Documentation/arm64/sve.rst
@@ -175,7 +175,7 @@ the SVE instruction set architecture.
 When returning from a signal handler:
 
 * If there is no sve_context record in the signal frame, or if the record is
-  present but contains no register data as desribed in the previous section,
+  present but contains no register data as described in the previous section,
   then the SVE registers/bits become non-live and take unspecified values.
 
 * If sve_context is present in the signal frame and contains full register
@@ -223,7 +223,7 @@ prctl(PR_SVE_SET_VL, unsigned long arg)
 	    Defer the requested vector length change until the next execve()
 	    performed by this thread.
 
-	    The effect is equivalent to implicit exceution of the following
+	    The effect is equivalent to implicit execution of the following
 	    call immediately after the next execve() (if any) by the thread:
 
 		prctl(PR_SVE_SET_VL, arg & ~PR_SVE_SET_VL_ONEXEC)

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Re: [PATCH 01/35] Documentation: arm64: correct spelling

[Mukesh Ojha]

On 1/27/2023 12:09 PM, Randy Dunlap wrote:
> Correct spelling problems for Documentation/arm64/ as reported
> by codespell.
> 
> Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: Jonathan Corbet <corbet@lwn.net>
> Cc: linux-doc@vger.kernel.org
> ---
>   Documentation/arm64/booting.rst    |    2 +-
>   Documentation/arm64/elf_hwcaps.rst |    2 +-
>   Documentation/arm64/sve.rst        |    4 ++--
>   3 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff -- a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
> --- a/Documentation/arm64/booting.rst
> +++ b/Documentation/arm64/booting.rst
> @@ -223,7 +223,7 @@ Before jumping into the kernel, the foll
>     For systems with a GICv3 interrupt controller to be used in v3 mode:
>     - If EL3 is present:
>   
> -      - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.
> +      - ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1.
>         - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
>         - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
>           all CPUs the kernel is executing on, and must stay constant
> diff -- a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst
> --- a/Documentation/arm64/elf_hwcaps.rst
> +++ b/Documentation/arm64/elf_hwcaps.rst
> @@ -14,7 +14,7 @@ Some hardware or software features are o
>   implementations, and/or with certain kernel configurations, but have no
>   architected discovery mechanism available to userspace code at EL0. The
>   kernel exposes the presence of these features to userspace through a set
> -of flags called hwcaps, exposed in the auxilliary vector.
> +of flags called hwcaps, exposed in the auxiliary vector.
>   
>   Userspace software can test for features by acquiring the AT_HWCAP or
>   AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant
> diff -- a/Documentation/arm64/sve.rst b/Documentation/arm64/sve.rst
> --- a/Documentation/arm64/sve.rst
> +++ b/Documentation/arm64/sve.rst
> @@ -175,7 +175,7 @@ the SVE instruction set architecture.
>   When returning from a signal handler:
>   
>   * If there is no sve_context record in the signal frame, or if the record is
> -  present but contains no register data as desribed in the previous section,
> +  present but contains no register data as described in the previous section,
>     then the SVE registers/bits become non-live and take unspecified values.
>   
>   * If sve_context is present in the signal frame and contains full register
> @@ -223,7 +223,7 @@ prctl(PR_SVE_SET_VL, unsigned long arg)
>   	    Defer the requested vector length change until the next execve()
>   	    performed by this thread.
>   
> -	    The effect is equivalent to implicit exceution of the following
> +	    The effect is equivalent to implicit execution of the following
>   	    call immediately after the next execve() (if any) by the thread:
>   
>   		prctl(PR_SVE_SET_VL, arg & ~PR_SVE_SET_VL_ONEXEC)
> 

Reviewed-by: Mukesh Ojha <quic_mojha@quicinc.com>

-Mukesh

> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

_______________________________________________
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[PATCH 31/35] Documentation: trace: correct spelling

[Randy Dunlap]

Correct spelling problems for Documentation/trace/ as reported
by codespell.

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Masami Hiramatsu <mhiramat@kernel.org>
Cc: Daniel Bristot de Oliveira <bristot@kernel.org>
Cc: linux-trace-kernel@vger.kernel.org
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: linux-doc@vger.kernel.org
---
 Documentation/trace/coresight/coresight-etm4x-reference.rst |    2 +-
 Documentation/trace/events.rst                              |    6 +++---
 Documentation/trace/fprobe.rst                              |    2 +-
 Documentation/trace/ftrace-uses.rst                         |    2 +-
 Documentation/trace/hwlat_detector.rst                      |    2 +-
 Documentation/trace/rv/runtime-verification.rst             |    2 +-
 Documentation/trace/uprobetracer.rst                        |    2 +-
 7 files changed, 9 insertions(+), 9 deletions(-)

diff -- a/Documentation/trace/coresight/coresight-etm4x-reference.rst b/Documentation/trace/coresight/coresight-etm4x-reference.rst
--- a/Documentation/trace/coresight/coresight-etm4x-reference.rst
+++ b/Documentation/trace/coresight/coresight-etm4x-reference.rst
@@ -675,7 +675,7 @@ Bit assignments shown below:-
     reconstructed using only conditional branches.
 
     There is currently no support in Perf for supplying modified binaries to the decoder, so this
-    feature is only inteded to be used for debugging purposes or with a 3rd party tool.
+    feature is only intended to be used for debugging purposes or with a 3rd party tool.
 
     Choosing this option will result in a significant increase in the amount of trace generated -
     possible danger of overflows, or fewer instructions covered. Note, that this option also
diff -- a/Documentation/trace/events.rst b/Documentation/trace/events.rst
--- a/Documentation/trace/events.rst
+++ b/Documentation/trace/events.rst
@@ -903,7 +903,7 @@ functions can be used.
 
 To create a kprobe event, an empty or partially empty kprobe event
 should first be created using kprobe_event_gen_cmd_start().  The name
-of the event and the probe location should be specfied along with one
+of the event and the probe location should be specified along with one
 or args each representing a probe field should be supplied to this
 function.  Before calling kprobe_event_gen_cmd_start(), the user
 should create and initialize a dynevent_cmd object using
@@ -983,7 +983,7 @@ The basic idea is simple and amounts to
 layer that can be used to generate trace event commands.  The
 generated command strings can then be passed to the command-parsing
 and event creation code that already exists in the trace event
-subystem for creating the corresponding trace events.
+subsystem for creating the corresponding trace events.
 
 In a nutshell, the way it works is that the higher-level interface
 code creates a struct dynevent_cmd object, then uses a couple
@@ -1056,7 +1056,7 @@ to add an operator between the pair (her
 appended onto the end of the arg pair (here ';').
 
 There's also a dynevent_str_add() function that can be used to simply
-add a string as-is, with no spaces, delimeters, or arg check.
+add a string as-is, with no spaces, delimiters, or arg check.
 
 Any number of dynevent_*_add() calls can be made to build up the string
 (until its length surpasses cmd->maxlen).  When all the arguments have
diff -- a/Documentation/trace/fprobe.rst b/Documentation/trace/fprobe.rst
--- a/Documentation/trace/fprobe.rst
+++ b/Documentation/trace/fprobe.rst
@@ -111,7 +111,7 @@ saved at function entry and passed to ex
         the instruction pointer of @regs may be different from the @entry_ip
         in the entry_handler. If you need traced instruction pointer, you need
         to use @entry_ip. On the other hand, in the exit_handler, the instruction
-        pointer of @regs is set to the currect return address.
+        pointer of @regs is set to the correct return address.
 
 Share the callbacks with kprobes
 ================================
diff -- a/Documentation/trace/ftrace-uses.rst b/Documentation/trace/ftrace-uses.rst
--- a/Documentation/trace/ftrace-uses.rst
+++ b/Documentation/trace/ftrace-uses.rst
@@ -193,7 +193,7 @@ FTRACE_OPS_FL_RECURSION
 	Not, if this flag is set, then the callback will always be called
 	with preemption disabled. If it is not set, then it is possible
 	(but not guaranteed) that the callback will be called in
-	preemptable context.
+	preemptible context.
 
 FTRACE_OPS_FL_IPMODIFY
 	Requires FTRACE_OPS_FL_SAVE_REGS set. If the callback is to "hijack"
diff -- a/Documentation/trace/hwlat_detector.rst b/Documentation/trace/hwlat_detector.rst
--- a/Documentation/trace/hwlat_detector.rst
+++ b/Documentation/trace/hwlat_detector.rst
@@ -14,7 +14,7 @@ originally written for use by the "RT" p
 kernel is highly latency sensitive.
 
 SMIs are not serviced by the Linux kernel, which means that it does not
-even know that they are occuring. SMIs are instead set up by BIOS code
+even know that they are occurring. SMIs are instead set up by BIOS code
 and are serviced by BIOS code, usually for "critical" events such as
 management of thermal sensors and fans. Sometimes though, SMIs are used for
 other tasks and those tasks can spend an inordinate amount of time in the
diff -- a/Documentation/trace/rv/runtime-verification.rst b/Documentation/trace/rv/runtime-verification.rst
--- a/Documentation/trace/rv/runtime-verification.rst
+++ b/Documentation/trace/rv/runtime-verification.rst
@@ -31,7 +31,7 @@ In Linux terms, the runtime verification
 *RV monitor* abstraction. A *RV monitor* includes a reference model of the
 system, a set of instances of the monitor (per-cpu monitor, per-task monitor,
 and so on), and the helper functions that glue the monitor to the system via
-trace, as depicted bellow::
+trace, as depicted below::
 
  Linux   +---- RV Monitor ----------------------------------+ Formal
   Realm  |                                                  |  Realm
diff -- a/Documentation/trace/uprobetracer.rst b/Documentation/trace/uprobetracer.rst
--- a/Documentation/trace/uprobetracer.rst
+++ b/Documentation/trace/uprobetracer.rst
@@ -55,7 +55,7 @@ Synopsis of uprobe_tracer
 
   (\*1) only for return probe.
   (\*2) this is useful for fetching a field of data structures.
-  (\*3) Unlike kprobe event, "u" prefix will just be ignored, becuse uprobe
+  (\*3) Unlike kprobe event, "u" prefix will just be ignored, because uprobe
         events can access only user-space memory.
 
 Types

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Re: [PATCH 31/35] Documentation: trace: correct spelling

[Mukesh Ojha]

On 1/27/2023 12:10 PM, Randy Dunlap wrote:
> Correct spelling problems for Documentation/trace/ as reported
> by codespell.
> 
> Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
> Cc: Steven Rostedt <rostedt@goodmis.org>
> Cc: Masami Hiramatsu <mhiramat@kernel.org>
> Cc: Daniel Bristot de Oliveira <bristot@kernel.org>
> Cc: linux-trace-kernel@vger.kernel.org
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: coresight@lists.linaro.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: Jonathan Corbet <corbet@lwn.net>
> Cc: linux-doc@vger.kernel.org
> ---
>   Documentation/trace/coresight/coresight-etm4x-reference.rst |    2 +-
>   Documentation/trace/events.rst                              |    6 +++---
>   Documentation/trace/fprobe.rst                              |    2 +-
>   Documentation/trace/ftrace-uses.rst                         |    2 +-
>   Documentation/trace/hwlat_detector.rst                      |    2 +-
>   Documentation/trace/rv/runtime-verification.rst             |    2 +-
>   Documentation/trace/uprobetracer.rst                        |    2 +-
>   7 files changed, 9 insertions(+), 9 deletions(-)
> 
> diff -- a/Documentation/trace/coresight/coresight-etm4x-reference.rst b/Documentation/trace/coresight/coresight-etm4x-reference.rst
> --- a/Documentation/trace/coresight/coresight-etm4x-reference.rst
> +++ b/Documentation/trace/coresight/coresight-etm4x-reference.rst
> @@ -675,7 +675,7 @@ Bit assignments shown below:-
>       reconstructed using only conditional branches.
>   
>       There is currently no support in Perf for supplying modified binaries to the decoder, so this
> -    feature is only inteded to be used for debugging purposes or with a 3rd party tool.
> +    feature is only intended to be used for debugging purposes or with a 3rd party tool.
>   
>       Choosing this option will result in a significant increase in the amount of trace generated -
>       possible danger of overflows, or fewer instructions covered. Note, that this option also
> diff -- a/Documentation/trace/events.rst b/Documentation/trace/events.rst
> --- a/Documentation/trace/events.rst
> +++ b/Documentation/trace/events.rst
> @@ -903,7 +903,7 @@ functions can be used.
>   
>   To create a kprobe event, an empty or partially empty kprobe event
>   should first be created using kprobe_event_gen_cmd_start().  The name
> -of the event and the probe location should be specfied along with one
> +of the event and the probe location should be specified along with one
>   or args each representing a probe field should be supplied to this
>   function.  Before calling kprobe_event_gen_cmd_start(), the user
>   should create and initialize a dynevent_cmd object using
> @@ -983,7 +983,7 @@ The basic idea is simple and amounts to
>   layer that can be used to generate trace event commands.  The
>   generated command strings can then be passed to the command-parsing
>   and event creation code that already exists in the trace event
> -subystem for creating the corresponding trace events.
> +subsystem for creating the corresponding trace events.
>   
>   In a nutshell, the way it works is that the higher-level interface
>   code creates a struct dynevent_cmd object, then uses a couple
> @@ -1056,7 +1056,7 @@ to add an operator between the pair (her
>   appended onto the end of the arg pair (here ';').
>   
>   There's also a dynevent_str_add() function that can be used to simply
> -add a string as-is, with no spaces, delimeters, or arg check.
> +add a string as-is, with no spaces, delimiters, or arg check.
>   
>   Any number of dynevent_*_add() calls can be made to build up the string
>   (until its length surpasses cmd->maxlen).  When all the arguments have
> diff -- a/Documentation/trace/fprobe.rst b/Documentation/trace/fprobe.rst
> --- a/Documentation/trace/fprobe.rst
> +++ b/Documentation/trace/fprobe.rst
> @@ -111,7 +111,7 @@ saved at function entry and passed to ex
>           the instruction pointer of @regs may be different from the @entry_ip
>           in the entry_handler. If you need traced instruction pointer, you need
>           to use @entry_ip. On the other hand, in the exit_handler, the instruction
> -        pointer of @regs is set to the currect return address.
> +        pointer of @regs is set to the correct return address.
>   
>   Share the callbacks with kprobes
>   ================================
> diff -- a/Documentation/trace/ftrace-uses.rst b/Documentation/trace/ftrace-uses.rst
> --- a/Documentation/trace/ftrace-uses.rst
> +++ b/Documentation/trace/ftrace-uses.rst
> @@ -193,7 +193,7 @@ FTRACE_OPS_FL_RECURSION
>   	Not, if this flag is set, then the callback will always be called
>   	with preemption disabled. If it is not set, then it is possible
>   	(but not guaranteed) that the callback will be called in
> -	preemptable context.
> +	preemptible context.
>   
>   FTRACE_OPS_FL_IPMODIFY
>   	Requires FTRACE_OPS_FL_SAVE_REGS set. If the callback is to "hijack"
> diff -- a/Documentation/trace/hwlat_detector.rst b/Documentation/trace/hwlat_detector.rst
> --- a/Documentation/trace/hwlat_detector.rst
> +++ b/Documentation/trace/hwlat_detector.rst
> @@ -14,7 +14,7 @@ originally written for use by the "RT" p
>   kernel is highly latency sensitive.
>   
>   SMIs are not serviced by the Linux kernel, which means that it does not
> -even know that they are occuring. SMIs are instead set up by BIOS code
> +even know that they are occurring. SMIs are instead set up by BIOS code
>   and are serviced by BIOS code, usually for "critical" events such as
>   management of thermal sensors and fans. Sometimes though, SMIs are used for
>   other tasks and those tasks can spend an inordinate amount of time in the
> diff -- a/Documentation/trace/rv/runtime-verification.rst b/Documentation/trace/rv/runtime-verification.rst
> --- a/Documentation/trace/rv/runtime-verification.rst
> +++ b/Documentation/trace/rv/runtime-verification.rst
> @@ -31,7 +31,7 @@ In Linux terms, the runtime verification
>   *RV monitor* abstraction. A *RV monitor* includes a reference model of the
>   system, a set of instances of the monitor (per-cpu monitor, per-task monitor,
>   and so on), and the helper functions that glue the monitor to the system via
> -trace, as depicted bellow::
> +trace, as depicted below::
>   
>    Linux   +---- RV Monitor ----------------------------------+ Formal
>     Realm  |                                                  |  Realm
> diff -- a/Documentation/trace/uprobetracer.rst b/Documentation/trace/uprobetracer.rst
> --- a/Documentation/trace/uprobetracer.rst
> +++ b/Documentation/trace/uprobetracer.rst
> @@ -55,7 +55,7 @@ Synopsis of uprobe_tracer
>   
>     (\*1) only for return probe.
>     (\*2) this is useful for fetching a field of data structures.
> -  (\*3) Unlike kprobe event, "u" prefix will just be ignored, becuse uprobe
> +  (\*3) Unlike kprobe event, "u" prefix will just be ignored, because uprobe
>           events can access only user-space memory.
>   
>   Types


Reviewed-by: Mukesh Ojha <quic_mojha@quicinc.com>

-Mukesh
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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Re: [PATCH 31/35] Documentation: trace: correct spelling

[Daniel Bristot de Oliveira]

On 1/27/23 07:40, Randy Dunlap wrote:
> --- a/Documentation/trace/rv/runtime-verification.rst
> +++ b/Documentation/trace/rv/runtime-verification.rst
> @@ -31,7 +31,7 @@ In Linux terms, the runtime verification
>  *RV monitor* abstraction. A *RV monitor* includes a reference model of the
>  system, a set of instances of the monitor (per-cpu monitor, per-task monitor,
>  and so on), and the helper functions that glue the monitor to the system via
> -trace, as depicted bellow::
> +trace, as depicted below::
>  
>   Linux   +---- RV Monitor ----------------------------------+ Formal
>    Realm  |                                                  |  Realm

Do you mind making the rv part an independent patch?

Spiting it helps in the backport of the fix to stable/distro kernels.

-- Daniel

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Re: [PATCH 31/35] Documentation: trace: correct spelling

[Randy Dunlap]

On 1/27/23 00:54, Daniel Bristot de Oliveira wrote:
> On 1/27/23 07:40, Randy Dunlap wrote:
>> --- a/Documentation/trace/rv/runtime-verification.rst
>> +++ b/Documentation/trace/rv/runtime-verification.rst
>> @@ -31,7 +31,7 @@ In Linux terms, the runtime verification
>>  *RV monitor* abstraction. A *RV monitor* includes a reference model of the
>>  system, a set of instances of the monitor (per-cpu monitor, per-task monitor,
>>  and so on), and the helper functions that glue the monitor to the system via
>> -trace, as depicted bellow::
>> +trace, as depicted below::
>>  
>>   Linux   +---- RV Monitor ----------------------------------+ Formal
>>    Realm  |                                                  |  Realm
> 
> Do you mind making the rv part an independent patch?
> 
> Spiting it helps in the backport of the fix to stable/distro kernels.

I wouldn't expect this to be packported. stable-kernel-rules.rst says:

 - It cannot contain any "trivial" fixes in it (spelling changes,
   whitespace cleanups, etc).

-- 
~Randy

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Re: [PATCH 31/35] Documentation: trace: correct spelling

[Steven Rostedt]

On Thu, 26 Jan 2023 22:40:01 -0800
Randy Dunlap <rdunlap@infradead.org> wrote:

> Correct spelling problems for Documentation/trace/ as reported
> by codespell.
> 
> Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
> Cc: Steven Rostedt <rostedt@goodmis.org>
> Cc: Masami Hiramatsu <mhiramat@kernel.org>
> Cc: Daniel Bristot de Oliveira <bristot@kernel.org>
> Cc: linux-trace-kernel@vger.kernel.org
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: coresight@lists.linaro.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: Jonathan Corbet <corbet@lwn.net>
> Cc: linux-doc@vger.kernel.org
> ---

Acked-by: Steven Rostedt (Google) <rostedt@goodmis.org>

-- Steve

>  Documentation/trace/coresight/coresight-etm4x-reference.rst |    2 +-
>  Documentation/trace/events.rst                              |    6 +++---
>  Documentation/trace/fprobe.rst                              |    2 +-
>  Documentation/trace/ftrace-uses.rst                         |    2 +-
>  Documentation/trace/hwlat_detector.rst                      |    2 +-
>  Documentation/trace/rv/runtime-verification.rst             |    2 +-
>  Documentation/trace/uprobetracer.rst                        |    2 +-
>  7 files changed, 9 insertions(+), 9 deletions(-)
> 

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Re: [PATCH 31/35] Documentation: trace: correct spelling

[Suzuki K Poulose]

On 27/01/2023 06:40, Randy Dunlap wrote:
> Correct spelling problems for Documentation/trace/ as reported
> by codespell.
> 
> Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
> Cc: Steven Rostedt <rostedt@goodmis.org>
> Cc: Masami Hiramatsu <mhiramat@kernel.org>
> Cc: Daniel Bristot de Oliveira <bristot@kernel.org>
> Cc: linux-trace-kernel@vger.kernel.org
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: coresight@lists.linaro.org
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: Jonathan Corbet <corbet@lwn.net>
> Cc: linux-doc@vger.kernel.org
> ---
>   Documentation/trace/coresight/coresight-etm4x-reference.rst |    2 +-
>   Documentation/trace/events.rst                              |    6 +++---
>   Documentation/trace/fprobe.rst                              |    2 +-
>   Documentation/trace/ftrace-uses.rst                         |    2 +-
>   Documentation/trace/hwlat_detector.rst                      |    2 +-
>   Documentation/trace/rv/runtime-verification.rst             |    2 +-
>   Documentation/trace/uprobetracer.rst                        |    2 +-
>   7 files changed, 9 insertions(+), 9 deletions(-)
> 
> diff -- a/Documentation/trace/coresight/coresight-etm4x-reference.rst b/Documentation/trace/coresight/coresight-etm4x-reference.rst
> --- a/Documentation/trace/coresight/coresight-etm4x-reference.rst
> +++ b/Documentation/trace/coresight/coresight-etm4x-reference.rst
> @@ -675,7 +675,7 @@ Bit assignments shown below:-
>       reconstructed using only conditional branches.
>   
>       There is currently no support in Perf for supplying modified binaries to the decoder, so this
> -    feature is only inteded to be used for debugging purposes or with a 3rd party tool.
> +    feature is only intended to be used for debugging purposes or with a 3rd party tool.
>   
>       Choosing this option will result in a significant increase in the amount of trace generated -
>       possible danger of overflows, or fewer instructions covered. Note, that this option also

For the above:

Acked-by: Suzuki K Poulose <suzuki.poulose@arm.com>

Thanks
Suzuki

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