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From: tarunsahu@google.com
To: Pasha Tatashin <pasha.tatashin@soleen.com>,
	Pratyush Yadav <pratyush@kernel.org>,
	 Mike Rapoport <rppt@kernel.org>,
	will@kernel.org, changyuanl@google.com,
	 Alexander Graf <graf@amazon.com>,
	mark.rutland@arm.com, jgg@nvidia.com
Cc: linux-arm-kernel@lists.infradead.org, kexec@lists.infradead.org
Subject: QNS: ARM64: Cache coherency while doing Kexec for KHO
Date: Tue, 11 Aug 2026 19:19:11 +0000	[thread overview]
Message-ID: <9huzldaczcr4.fsf@tarunix.c.googlers.com> (raw)


Hi,

I have a question regarding cache maintenance for Kernel Handover (KHO)
preserved memory across kexec reboots on arm64.

During kexec, all other CPUs gets hot-unplugged where they flush all
of their caches so there will be no issues with any KHO data preserved
having caches on these CPUs.

But CPU0 still has not been flushed its D-cache (Is this correct?) and
it will only do flushing for specific area by kexec_segment_flush().

So for KHO preserved memory, if its caches still marked dirty on CPU0
they will not be flushed?

Is my understanding correct? or AM I missing something?
Also if this true, This will be a problem?

PS: Pardon my less knowledge on ARM64 cache coherency.

~Tarun


             reply	other threads:[~2026-08-11 19:19 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-11 19:19 tarunsahu [this message]
2026-08-11 19:23 ` QNS: ARM64: Cache coherency while doing Kexec for KHO tarunsahu
2026-08-11 19:30 ` Jason Gunthorpe

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