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Tue, 27 Oct 2026 03:22:27 -0700 (PDT) Received: from smtpclient.apple ([87.200.95.144]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e3ebd4be6sm20023565f8f.37.2026.10.27.03.22.22 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Oct 2026 03:22:25 -0700 (PDT) Content-Type: text/plain; charset=utf-8 X-Archived-By: Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3864.700.51.1.3\)) Subject: Re: [PATCH 4/4] cpufreq: add an Amlogic speed-bin driver From: Christian Hewitt In-Reply-To: <9556e959-daf3-4c85-8794-9613e7e7a9ae@gmail.com> Date: Tue, 27 Oct 2026 14:22:09 +0400 Cc: Viresh Kumar , Jerome Brunet , christian.koever-draxl@student.uibk.ac.at, neil.armstrong@linaro.org, sboyd@kernel.org, bmasney+clk@redhat.com, khilman@baylibre.com, martin.blumenstingl@googlemail.com, rafael@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-kernel@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?Q?Christian_Stefan_K=C3=B6v=C3=A9r-Draxl?= Content-Transfer-Encoding: quoted-printable Message-Id: References: <20261025192219.209137-1-christian.koever-draxl@student.uibk.ac.at> <20261025192219.209137-5-christian.koever-draxl@student.uibk.ac.at> <1jbj8gkff1.fsf@starbuckisacylon.baylibre.com> <9556e959-daf3-4c85-8794-9613e7e7a9ae@gmail.com> To: Chuan Liu X-Mailer: Apple Mail (2.3864.700.51.1.3) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261027_032229_798070_3E059005 X-CRM114-Status: GOOD ( 22.86 ) X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-17.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FORGED_FROMDOMAIN, FREEMAIL_FROM,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 > On 27 Oct 2026, at 1:26=E2=80=AFpm, Chuan Liu = wrote: >=20 > Hi Viresh, Christian, > Could you please hold off for now on the patches adding cpufreq = driver support on S4? There are still two issues that need to be = resolved first: > - The clock driver currently does not support setting the CPU clock. > - The CPU regulator needs some time to stabilize after the voltage is = changed. Without a proper delay, the CPU clock frequency may be raised = before the regulator voltage has actually reached the target value, = which can hang the system. The S4 CPU regulator handling currently lacks = the logic to wait for the regulator voltage to settle, so this part = needs to be completed first. >=20 > We are currently working on submitting our own cpufreq driver. We are = considering how to address the issues above, taking into account the = hardware characteristics of previous SoCs and evaluating factors such as = the transition latency. S4 will be covered by that work (as well as SoCs = from S4 onward, such as C3, T7, ..., A9). So please give us some time. Please don=E2=80=99t top-post, keep inline threading! FWIW, the recent bindings/clock/driver work I=E2=80=99ve done for S4 is = here: https://github.com/chewitt/linux/commits/amlogic-7.3.y My speed-bin driver is based on earlier work from Martin Blumenstingl: = https://github.com/chewitt/linux/commit/77e12d4d584d6a8bbd93304bbd4e9bbbb6= ee159a Setting a ramp-delay was the key to opp transition stability: = https://github.com/chewitt/linux/commit/ca7a99e86e23677c7b5af887e6f3b3c8ce= 3470d2 CH. also a Christian, to confuse people :) > On 10/26/2026 4:59 PM, Viresh Kumar wrote: >> On 26-10-26, 09:57, Jerome Brunet wrote: >>> On lun. 26 oct. 2026 at 11:00, Viresh Kumar = wrote: >>>=20 >>>> On 25-10-26, 20:22, christian.koever-draxl@student.uibk.ac.at = wrote: >>>>> From: Christian Stefan K=C3=B6v=C3=A9r-Draxl >>>>>=20 >>>>> Every S4 speed bin runs the same CPU frequencies but needs its own >>>>> voltage curve, and the bin can only be read through the secure = monitor. >>>>>=20 >>>>> Read the bin from the firmware, select the matching >>>>> "opp-microvolt-speed" property for all CPUs, then register >>>>> cpufreq-dt. Bins outside the known range fall back to bin 0, which >>>>> has the highest voltages. Like sun50i-cpufreq-nvmem, the driver = binds >>>>> on the SoC compatible and needs no node of its own, and S4 is = added to >>>>> the cpufreq-dt-platdev blocklist so cpufreq-dt is only created = after >>>>> the bin has been applied. >>>>>=20 >>>>> Signed-off-by: Christian Stefan K=C3=B6v=C3=A9r-Draxl = >>>>> --- >>>>> MAINTAINERS | 1 + >>>>> drivers/cpufreq/Kconfig.arm | 14 ++ >>>>> drivers/cpufreq/Makefile | 1 + >>>>> drivers/cpufreq/amlogic-cpufreq.c | 184 = +++++++++++++++++++++++++++ >>>>> drivers/cpufreq/cpufreq-dt-platdev.c | 2 + >>>>> 5 files changed, 202 insertions(+) >>>>> create mode 100644 drivers/cpufreq/amlogic-cpufreq.c >>>>=20 >>>> Is it safe to apply just this one ? I can take this via the PM tree = then. >>>=20 >>> I would advise to wait a little for Amlogic to chime in. >> Sure, I wasn't going to wait for the maintainers to respond anyway. >=20 > --=20 > Best regards, > Chuan >=20 >=20 > _______________________________________________ > linux-amlogic mailing list > linux-amlogic@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-amlogic