From mboxrd@z Thu Jan  1 00:00:00 1970
From: catalin.marinas@arm.com (Catalin Marinas)
Date: Sat, 19 Feb 2011 23:16:56 +0000
Subject: [PATCH v4 12/19] ARM: LPAE: Add context switching support
In-Reply-To: <20110219183027.GT29493@n2100.arm.linux.org.uk>
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	<1295891761-18366-13-git-send-email-catalin.marinas@arm.com>
	<20110212104400.GF15616@n2100.arm.linux.org.uk>
	<1297689846.31111.43.camel@e102109-lin.cambridge.arm.com>
	<20110219183027.GT29493@n2100.arm.linux.org.uk>
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To: linux-arm-kernel@lists.infradead.org
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On Saturday, 19 February 2011, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Mon, Feb 14, 2011 at 01:24:06PM +0000, Catalin Marinas wrote:
>> On Sat, 2011-02-12 at 10:44 +0000, Russell King - ARM Linux wrote:
>> > On Mon, Jan 24, 2011 at 05:55:54PM +0000, Catalin Marinas wrote:
>> > > +#ifdef CONFIG_ARM_LPAE
>> > > +#define cpu_set_asid(asid) { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> > > + ? ? unsigned long ttbl, ttbh; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> > > + ? ? asm(" ? mrrc ? ?p15, 0, %0, %1, c2 ? ? ? ? ? ? ?@ read TTBR0\n" \
>> > > + ? ? ? ? " ? mov ? ? %1, %1, lsl #(48 - 32) ? ? ? ? ?@ set ASID\n" ? \
>> > > + ? ? ? ? " ? mcrr ? ?p15, 0, %0, %1, c2 ? ? ? ? ? ? ?@ set TTBR0\n" ?\
>> > > + ? ? ? ? : "=r" (ttbl), "=r" (ttbh) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> > > + ? ? ? ? : "r" (asid & ~ASID_MASK)); ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> >
>> > This is wrong:
>> > 1. It does nothing with %2 (the new asid)
>> > 2. it shifts the high address bits of TTBR0 left 16 places each time its
>> > ? ?called.
>>
>> It was worse actually, not even compiled in because it had output
>> arguments but it wasn't volatile. Some early clobber is also needed.
>> What about this:
>>
>> #define cpu_set_asid(asid) { ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> ? ? ? unsigned long ttbl, ttbh; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> ? ? ? asm volatile( ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> ? ? ? " ? ? ? mrrc ? ?p15, 0, %0, %1, c2 ? ? ? ? ? ? ?@ read TTBR0\n" \
>> ? ? ? " ? ? ? mov ? ? %1, %2, lsl #(48 - 32) ? ? ? ? ?@ set ASID\n" ? \
>> ? ? ? " ? ? ? mcrr ? ?p15, 0, %0, %1, c2 ? ? ? ? ? ? ?@ set TTBR0\n" ?\
>> ? ? ? : "=&r" (ttbl), "=&r" (ttbh) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
>> ? ? ? : "r" (asid & ~ASID_MASK)); ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
>> }
>
> So we don't care about the low 16 bits of ttbh which can be simply zeroed?

Since the pgd is always allocated from lowmem, it is within 32-bit of
physical address and we can safely ignore ttbh. I could write a
comment here to this.

Catalin

-- 
Catalin