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[209.85.210.44]) by smtp.gmail.com with ESMTPSA id z26-20020a0568301dba00b005ad0fc5abe4sm2740182oti.16.2022.03.04.12.47.36 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 04 Mar 2022 12:47:37 -0800 (PST) Received: by mail-ot1-f44.google.com with SMTP id j8-20020a056830014800b005ad00ef6d5dso8407305otp.0 for ; Fri, 04 Mar 2022 12:47:36 -0800 (PST) X-Received: by 2002:a9d:7:0:b0:5b1:fe36:2d15 with SMTP id 7-20020a9d0007000000b005b1fe362d15mr249673ota.186.1646426856478; Fri, 04 Mar 2022 12:47:36 -0800 (PST) MIME-Version: 1.0 References: <20220127230727.3369358-1-briannorris@chromium.org> <20220127150615.v2.12.I3a5c7f21ecd8221b42c2dbcd618386bce7b3e9a6@changeid> In-Reply-To: From: Brian Norris Date: Fri, 4 Mar 2022 12:47:25 -0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v2 12/15] arm64: dts: rockchip: Enable dmc and dfi nodes on gru To: Peter Geis Cc: MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Rob Herring , Linux Kernel Mailing List , "open list:ARM/Rockchip SoC..." , Lin Huang , arm-mail-list , Derek Basehore , devicetree , linux-pm , Heiko Stuebner , Enric Balletbo i Serra , =?UTF-8?B?R2HDq2wgUE9SVEFZ?= , Daniel Lezcano X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220304_124742_179970_5A69550C X-CRM114-Status: GOOD ( 21.21 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Peter, On Fri, Mar 4, 2022 at 6:47 AM Peter Geis wrote: > I'm trying to bring this series over to rockpro64 (and eventually the > pinephone-pro) and am running into some snags. Dumb question: is DDR DVFS supported on these systems in the "production" (vendor kernel? I'm not really familiar with these devices) software? I partly ask, because while I didn't do some of this first-hand, I'm aware that it was a real ordeal to get things stabilized (e.g., getting all the timings right; communicating the right details from bootloader to ATF; etc.), so if no one did these things in the first place, it's probably difficult to get working now just by guessing. But if it works on a customized kernel, then that's a different story. > Essentially, anytime a transition happens, the board locks up. > I've disabled the extra power save disable flags and adjusted the OPPs > for rockpro64's power. > Transitions anywhere from the default 800mhz cause a lock. > > I'm digging deeper, but I'm hoping you can answer some questions in > the meantime: > 1. Does this require something from firmware that isn't available on > Mainline ATF? (AKA special firmware to the Chromebook line) I don't know precisely. Chromebooks track mainline ATF, but somewhere before initial product launch, each platform gets its own firmware branch. On that firmware branch, we still try to stay in sync with mainline to some extent (e.g., submit to mainline and cherry-pick to branch), but it's not guaranteed. Anyway, you can inspect our code here: https://chromium.googlesource.com/chromiumos/third_party/arm-trusted-firmware/+log/refs/heads/firmware-gru-8785.B https://chromium.googlesource.com/chromiumos/third_party/coreboot/+log/refs/heads/firmware-gru-8785.B Brian _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel