* [PATCH v3 1/4] mtd: nand: allow compile test of MTD_NAND_PXA3xx
2015-10-15 7:17 [PATCH v3 0/4] mtd: pxa3xx_nand: rework the timing setup Antoine Tenart
@ 2015-10-15 7:17 ` Antoine Tenart
2015-10-15 9:12 ` kbuild test robot
2015-10-15 7:17 ` [PATCH v3 2/4] mtd: pxa3xx_nand: add helpers to setup the timings Antoine Tenart
` (3 subsequent siblings)
4 siblings, 1 reply; 15+ messages in thread
From: Antoine Tenart @ 2015-10-15 7:17 UTC (permalink / raw)
To: linux-arm-kernel
Allow compile test of the MTD_NAND_PXA3xx nand driver.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
---
drivers/mtd/nand/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 3324281d1f53..0d3b7c442928 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -329,7 +329,7 @@ config MTD_NAND_ATMEL
config MTD_NAND_PXA3xx
tristate "NAND support on PXA3xx and Armada 370/XP"
- depends on PXA3xx || ARCH_MMP || PLAT_ORION
+ depends on PXA3xx || ARCH_MMP || PLAT_ORION || COMPILE_TEST
help
This enables the driver for the NAND flash device found on
PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
--
2.6.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 1/4] mtd: nand: allow compile test of MTD_NAND_PXA3xx
2015-10-15 7:17 ` [PATCH v3 1/4] mtd: nand: allow compile test of MTD_NAND_PXA3xx Antoine Tenart
@ 2015-10-15 9:12 ` kbuild test robot
2015-10-15 11:44 ` Arnd Bergmann
0 siblings, 1 reply; 15+ messages in thread
From: kbuild test robot @ 2015-10-15 9:12 UTC (permalink / raw)
To: linux-arm-kernel
Hi Antoine,
[auto build test ERROR on mtd/master -- if it's inappropriate base, please suggest rules for selecting the more suitable base]
url: https://github.com/0day-ci/linux/commits/Antoine-Tenart/mtd-pxa3xx_nand-rework-the-timing-setup/20151015-152337
config: i386-allmodconfig (attached as .config)
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All errors (new ones prefixed by >>):
drivers/mtd/nand/pxa3xx_nand.c: In function 'drain_fifo':
>> drivers/mtd/nand/pxa3xx_nand.c:507:4: error: implicit declaration of function 'readsl' [-Werror=implicit-function-declaration]
readsl(info->mmio_base + NDDB, data, 8);
^
drivers/mtd/nand/pxa3xx_nand.c: In function 'handle_data_pio':
>> drivers/mtd/nand/pxa3xx_nand.c:531:3: error: implicit declaration of function 'writesl' [-Werror=implicit-function-declaration]
writesl(info->mmio_base + NDDB,
^
cc1: some warnings being treated as errors
vim +/readsl +507 drivers/mtd/nand/pxa3xx_nand.c
8dad0386 Maxime Ripard 2015-02-18 501 * have to make sure that the NDSR.RDDREQ bit is set.
8dad0386 Maxime Ripard 2015-02-18 502 *
8dad0386 Maxime Ripard 2015-02-18 503 * Drain the FIFO 8 32 bits reads at a time, and skip
8dad0386 Maxime Ripard 2015-02-18 504 * the polling on the last read.
8dad0386 Maxime Ripard 2015-02-18 505 */
8dad0386 Maxime Ripard 2015-02-18 506 while (len > 8) {
ce914e6b Rob Herring 2015-04-30 @507 readsl(info->mmio_base + NDDB, data, 8);
8dad0386 Maxime Ripard 2015-02-18 508
afca11ec Maxime Ripard 2015-04-07 509 ret = readl_relaxed_poll_timeout(info->mmio_base + NDSR, val,
afca11ec Maxime Ripard 2015-04-07 510 val & NDSR_RDDREQ, 1000, 5000);
afca11ec Maxime Ripard 2015-04-07 511 if (ret) {
8dad0386 Maxime Ripard 2015-02-18 512 dev_err(&info->pdev->dev,
8dad0386 Maxime Ripard 2015-02-18 513 "Timeout on RDDREQ while draining the FIFO\n");
8dad0386 Maxime Ripard 2015-02-18 514 return;
8dad0386 Maxime Ripard 2015-02-18 515 }
8dad0386 Maxime Ripard 2015-02-18 516
8dad0386 Maxime Ripard 2015-02-18 517 data += 32;
8dad0386 Maxime Ripard 2015-02-18 518 len -= 8;
8dad0386 Maxime Ripard 2015-02-18 519 }
8dad0386 Maxime Ripard 2015-02-18 520 }
8dad0386 Maxime Ripard 2015-02-18 521
ce914e6b Rob Herring 2015-04-30 522 readsl(info->mmio_base + NDDB, data, len);
8dad0386 Maxime Ripard 2015-02-18 523 }
8dad0386 Maxime Ripard 2015-02-18 524
f8155a40 Lei Wen 2011-02-28 525 static void handle_data_pio(struct pxa3xx_nand_info *info)
fe69af00 eric miao 2008-02-14 526 {
70ed8523 Ezequiel Garcia 2013-11-14 527 unsigned int do_bytes = min(info->data_size, info->chunk_size);
fa543bef Ezequiel Garcia 2013-11-14 528
fe69af00 eric miao 2008-02-14 529 switch (info->state) {
fe69af00 eric miao 2008-02-14 530 case STATE_PIO_WRITING:
ce914e6b Rob Herring 2015-04-30 @531 writesl(info->mmio_base + NDDB,
fa543bef Ezequiel Garcia 2013-11-14 532 info->data_buff + info->data_buff_pos,
fa543bef Ezequiel Garcia 2013-11-14 533 DIV_ROUND_UP(do_bytes, 4));
fa543bef Ezequiel Garcia 2013-11-14 534
:::::: The code at line 507 was first introduced by commit
:::::: ce914e6b2658b9f1773ff57b3d45682a7ca4552f mtd: nand: pxa3xx: fix build on ARM64
:::::: TO: Rob Herring <robh@kernel.org>
:::::: CC: Brian Norris <computersforpeace@gmail.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v3 1/4] mtd: nand: allow compile test of MTD_NAND_PXA3xx
2015-10-15 9:12 ` kbuild test robot
@ 2015-10-15 11:44 ` Arnd Bergmann
2015-10-15 11:52 ` Antoine Tenart
0 siblings, 1 reply; 15+ messages in thread
From: Arnd Bergmann @ 2015-10-15 11:44 UTC (permalink / raw)
To: linux-arm-kernel
On Thursday 15 October 2015 17:12:18 kbuild test robot wrote:
> drivers/mtd/nand/pxa3xx_nand.c: In function 'drain_fifo':
> >> drivers/mtd/nand/pxa3xx_nand.c:507:4: error: implicit declaration of function 'readsl' [-Werror=implicit-function-declaration]
> readsl(info->mmio_base + NDDB, data, 8);
> ^
It should be easy to fix this by changing the code to use ioread32_rep() instead
of readsl(). They behave the same way on pointers returned from ioremap() etc,
and the other one is available on all architectures.
Arnd
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 1/4] mtd: nand: allow compile test of MTD_NAND_PXA3xx
2015-10-15 11:44 ` Arnd Bergmann
@ 2015-10-15 11:52 ` Antoine Tenart
0 siblings, 0 replies; 15+ messages in thread
From: Antoine Tenart @ 2015-10-15 11:52 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd,
On Thu, Oct 15, 2015 at 01:44:19PM +0200, Arnd Bergmann wrote:
> On Thursday 15 October 2015 17:12:18 kbuild test robot wrote:
> > drivers/mtd/nand/pxa3xx_nand.c: In function 'drain_fifo':
> > >> drivers/mtd/nand/pxa3xx_nand.c:507:4: error: implicit declaration of function 'readsl' [-Werror=implicit-function-declaration]
> > readsl(info->mmio_base + NDDB, data, 8);
> > ^
>
> It should be easy to fix this by changing the code to use ioread32_rep() instead
> of readsl(). They behave the same way on pointers returned from ioremap() etc,
> and the other one is available on all architectures.
Sure, I can add a patch fixing this prior to the one allowing to compile
test the pxa3xx nand driver.
Antoine
--
Antoine T?nart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 2/4] mtd: pxa3xx_nand: add helpers to setup the timings
2015-10-15 7:17 [PATCH v3 0/4] mtd: pxa3xx_nand: rework the timing setup Antoine Tenart
2015-10-15 7:17 ` [PATCH v3 1/4] mtd: nand: allow compile test of MTD_NAND_PXA3xx Antoine Tenart
@ 2015-10-15 7:17 ` Antoine Tenart
2015-10-17 13:57 ` Ezequiel Garcia
2015-10-15 7:17 ` [PATCH v3 3/4] mtd: pxa3xx_nand: rework flash detection and timing setup Antoine Tenart
` (2 subsequent siblings)
4 siblings, 1 reply; 15+ messages in thread
From: Antoine Tenart @ 2015-10-15 7:17 UTC (permalink / raw)
To: linux-arm-kernel
Add helpers to setup the timings in the pxa3xx driver. These helpers
allow to either make use of the nand framework nand_sdr_timings or the
pxa3xx specific pxa3xx_nand_host, for compatibility reasons.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
---
drivers/mtd/nand/pxa3xx_nand.c | 135 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 135 insertions(+)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 740983a34626..da52f21570cf 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -393,6 +393,128 @@ static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
nand_writel(info, NDTR1CS0, ndtr1);
}
+static void pxa3xx_nand_set_sdr_timing(struct pxa3xx_nand_host *host,
+ const struct nand_sdr_timings *t)
+{
+ struct pxa3xx_nand_info *info = host->info_data;
+ struct nand_chip *chip = &host->chip;
+ unsigned long nand_clk = clk_get_rate(info->clk);
+ uint32_t ndtr0, ndtr1;
+
+ u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000);
+ u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000);
+ u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000);
+ u32 tWP_min = DIV_ROUND_UP(t->tWC_min - t->tWH_min, 1000);
+ u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000);
+ u32 tRP_min = DIV_ROUND_UP(t->tRC_min - t->tREH_min, 1000);
+ u32 tR = chip->chip_delay * 1000;
+ u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000);
+ u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000);
+
+ /* fallback to a default value if tR = 0 */
+ if (!tR)
+ tR = 20000;
+
+ ndtr0 = NDTR0_tCH(ns2cycle(tCH_min, nand_clk)) |
+ NDTR0_tCS(ns2cycle(tCS_min, nand_clk)) |
+ NDTR0_tWH(ns2cycle(tWH_min, nand_clk)) |
+ NDTR0_tWP(ns2cycle(tWP_min, nand_clk)) |
+ NDTR0_tRH(ns2cycle(tREH_min, nand_clk)) |
+ NDTR0_tRP(ns2cycle(tRP_min, nand_clk));
+
+ ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) |
+ NDTR1_tWHR(ns2cycle(tWHR_min, nand_clk)) |
+ NDTR1_tAR(ns2cycle(tAR_min, nand_clk));
+
+ info->ndtr0cs0 = ndtr0;
+ info->ndtr1cs0 = ndtr1;
+ nand_writel(info, NDTR0CS0, ndtr0);
+ nand_writel(info, NDTR1CS0, ndtr1);
+}
+
+static int pxa3xx_nand_init_timings_compat(struct pxa3xx_nand_host *host,
+ unsigned int *flash_width,
+ unsigned int *dfc_width)
+{
+ struct nand_chip *chip = &host->chip;
+ struct pxa3xx_nand_info *info = host->info_data;
+ const struct pxa3xx_nand_flash *f = NULL;
+ int i, id, ntypes;
+
+ ntypes = ARRAY_SIZE(builtin_flash_types);
+
+ chip->cmdfunc(host->mtd, NAND_CMD_READID, 0x00, -1);
+
+ id = chip->read_byte(host->mtd);
+ id |= chip->read_byte(host->mtd) << 0x8;
+
+ for (i = 0; i < ntypes; i++) {
+ f = &builtin_flash_types[i];
+
+ if (f->chip_id == id)
+ break;
+ }
+
+ if (i == ntypes) {
+ dev_err(&info->pdev->dev, "Error: timings not found\n");
+ return -EINVAL;
+ }
+
+ pxa3xx_nand_set_timing(host, f->timing);
+
+ *flash_width = f->flash_width;
+ *dfc_width = f->dfc_width;
+
+ return 0;
+}
+
+static int pxa3xx_nand_init_timings_onfi(struct pxa3xx_nand_host *host,
+ int mode)
+{
+ const struct nand_sdr_timings *timings;
+
+ mode = fls(mode) - 1;
+ if (mode < 0)
+ mode = 0;
+
+ timings = onfi_async_timing_mode_to_sdr_timings(mode);
+ if (IS_ERR(timings))
+ return PTR_ERR(timings);
+
+ pxa3xx_nand_set_sdr_timing(host, timings);
+
+ return 0;
+}
+
+static int pxa3xx_nand_init(struct pxa3xx_nand_host *host)
+{
+ struct nand_chip *chip = &host->chip;
+ struct pxa3xx_nand_info *info = host->info_data;
+ unsigned int flash_width = 0, dfc_width = 0;
+ int mode, err;
+
+ mode = onfi_get_async_timing_mode(chip);
+ if (mode == ONFI_TIMING_MODE_UNKNOWN) {
+ err = pxa3xx_nand_init_timings_compat(host, &flash_width,
+ &dfc_width);
+ if (err)
+ return err;
+
+ if (flash_width == 16) {
+ info->reg_ndcr |= NDCR_DWIDTH_M;
+ chip->options |= NAND_BUSWIDTH_16;
+ }
+
+ info->reg_ndcr |= (dfc_width == 16) ? NDCR_DWIDTH_C : 0;
+ } else {
+ err = pxa3xx_nand_init_timings_onfi(host, mode);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
/*
* Set the data and OOB size, depending on the selected
* spare and ECC configuration.
@@ -1538,6 +1660,19 @@ KEEP_CONFIG:
if (nand_scan_ident(mtd, 1, def))
return -ENODEV;
+ if (!pdata->keep_config) {
+ ret = pxa3xx_nand_init(host);
+ if (ret) {
+ dev_err(&info->pdev->dev, "Failed to init nand: %d\n",
+ ret);
+ return ret;
+ }
+ }
+
+ ret = pxa3xx_nand_config_flash(info);
+ if (ret)
+ return ret;
+
if (pdata->flash_bbt) {
/*
* We'll use a bad block table stored in-flash and don't
--
2.6.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 2/4] mtd: pxa3xx_nand: add helpers to setup the timings
2015-10-15 7:17 ` [PATCH v3 2/4] mtd: pxa3xx_nand: add helpers to setup the timings Antoine Tenart
@ 2015-10-17 13:57 ` Ezequiel Garcia
2015-10-19 9:32 ` Antoine Tenart
0 siblings, 1 reply; 15+ messages in thread
From: Ezequiel Garcia @ 2015-10-17 13:57 UTC (permalink / raw)
To: linux-arm-kernel
Hi Antoine,
On 15 Oct 09:17 AM, Antoine Tenart wrote:
> Add helpers to setup the timings in the pxa3xx driver. These helpers
> allow to either make use of the nand framework nand_sdr_timings or the
> pxa3xx specific pxa3xx_nand_host, for compatibility reasons.
>
> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
> ---
> drivers/mtd/nand/pxa3xx_nand.c | 135 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 135 insertions(+)
>
> diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
> index 740983a34626..da52f21570cf 100644
> --- a/drivers/mtd/nand/pxa3xx_nand.c
> +++ b/drivers/mtd/nand/pxa3xx_nand.c
> @@ -393,6 +393,128 @@ static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
> nand_writel(info, NDTR1CS0, ndtr1);
> }
>
> +static void pxa3xx_nand_set_sdr_timing(struct pxa3xx_nand_host *host,
> + const struct nand_sdr_timings *t)
> +{
> + struct pxa3xx_nand_info *info = host->info_data;
> + struct nand_chip *chip = &host->chip;
> + unsigned long nand_clk = clk_get_rate(info->clk);
> + uint32_t ndtr0, ndtr1;
> +
> + u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000);
> + u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000);
> + u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000);
> + u32 tWP_min = DIV_ROUND_UP(t->tWC_min - t->tWH_min, 1000);
> + u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000);
> + u32 tRP_min = DIV_ROUND_UP(t->tRC_min - t->tREH_min, 1000);
> + u32 tR = chip->chip_delay * 1000;
> + u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000);
> + u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000);
> +
> + /* fallback to a default value if tR = 0 */
> + if (!tR)
> + tR = 20000;
> +
> + ndtr0 = NDTR0_tCH(ns2cycle(tCH_min, nand_clk)) |
> + NDTR0_tCS(ns2cycle(tCS_min, nand_clk)) |
> + NDTR0_tWH(ns2cycle(tWH_min, nand_clk)) |
> + NDTR0_tWP(ns2cycle(tWP_min, nand_clk)) |
> + NDTR0_tRH(ns2cycle(tREH_min, nand_clk)) |
> + NDTR0_tRP(ns2cycle(tRP_min, nand_clk));
> +
> + ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) |
> + NDTR1_tWHR(ns2cycle(tWHR_min, nand_clk)) |
> + NDTR1_tAR(ns2cycle(tAR_min, nand_clk));
> +
> + info->ndtr0cs0 = ndtr0;
> + info->ndtr1cs0 = ndtr1;
> + nand_writel(info, NDTR0CS0, ndtr0);
> + nand_writel(info, NDTR1CS0, ndtr1);
> +}
> +
> +static int pxa3xx_nand_init_timings_compat(struct pxa3xx_nand_host *host,
> + unsigned int *flash_width,
> + unsigned int *dfc_width)
> +{
> + struct nand_chip *chip = &host->chip;
> + struct pxa3xx_nand_info *info = host->info_data;
> + const struct pxa3xx_nand_flash *f = NULL;
> + int i, id, ntypes;
> +
> + ntypes = ARRAY_SIZE(builtin_flash_types);
> +
> + chip->cmdfunc(host->mtd, NAND_CMD_READID, 0x00, -1);
> +
> + id = chip->read_byte(host->mtd);
> + id |= chip->read_byte(host->mtd) << 0x8;
> +
> + for (i = 0; i < ntypes; i++) {
> + f = &builtin_flash_types[i];
> +
> + if (f->chip_id == id)
> + break;
> + }
> +
> + if (i == ntypes) {
> + dev_err(&info->pdev->dev, "Error: timings not found\n");
> + return -EINVAL;
> + }
> +
> + pxa3xx_nand_set_timing(host, f->timing);
> +
> + *flash_width = f->flash_width;
> + *dfc_width = f->dfc_width;
> +
> + return 0;
> +}
> +
> +static int pxa3xx_nand_init_timings_onfi(struct pxa3xx_nand_host *host,
> + int mode)
> +{
> + const struct nand_sdr_timings *timings;
> +
> + mode = fls(mode) - 1;
> + if (mode < 0)
> + mode = 0;
> +
> + timings = onfi_async_timing_mode_to_sdr_timings(mode);
> + if (IS_ERR(timings))
> + return PTR_ERR(timings);
> +
> + pxa3xx_nand_set_sdr_timing(host, timings);
> +
> + return 0;
> +}
> +
> +static int pxa3xx_nand_init(struct pxa3xx_nand_host *host)
> +{
> + struct nand_chip *chip = &host->chip;
> + struct pxa3xx_nand_info *info = host->info_data;
> + unsigned int flash_width = 0, dfc_width = 0;
> + int mode, err;
> +
> + mode = onfi_get_async_timing_mode(chip);
> + if (mode == ONFI_TIMING_MODE_UNKNOWN) {
> + err = pxa3xx_nand_init_timings_compat(host, &flash_width,
> + &dfc_width);
> + if (err)
> + return err;
> +
> + if (flash_width == 16) {
> + info->reg_ndcr |= NDCR_DWIDTH_M;
> + chip->options |= NAND_BUSWIDTH_16;
> + }
> +
> + info->reg_ndcr |= (dfc_width == 16) ? NDCR_DWIDTH_C : 0;
> + } else {
> + err = pxa3xx_nand_init_timings_onfi(host, mode);
> + if (err)
> + return err;
> + }
> +
> + return 0;
> +}
> +
> /*
> * Set the data and OOB size, depending on the selected
> * spare and ECC configuration.
> @@ -1538,6 +1660,19 @@ KEEP_CONFIG:
> if (nand_scan_ident(mtd, 1, def))
> return -ENODEV;
>
> + if (!pdata->keep_config) {
> + ret = pxa3xx_nand_init(host);
> + if (ret) {
> + dev_err(&info->pdev->dev, "Failed to init nand: %d\n",
> + ret);
> + return ret;
> + }
> + }
> +
> + ret = pxa3xx_nand_config_flash(info);
> + if (ret)
> + return ret;
> +
Does this chunk belong to this patch? It wasn't here in the v2, and I believe
it's not correct as you end up messing with the NDCR setting even if keep_config
was passed.
--
Ezequiel Garcia, VanguardiaSur
www.vanguardiasur.com.ar
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v3 2/4] mtd: pxa3xx_nand: add helpers to setup the timings
2015-10-17 13:57 ` Ezequiel Garcia
@ 2015-10-19 9:32 ` Antoine Tenart
0 siblings, 0 replies; 15+ messages in thread
From: Antoine Tenart @ 2015-10-19 9:32 UTC (permalink / raw)
To: linux-arm-kernel
Ezequiel,
On Sat, Oct 17, 2015 at 10:57:26AM -0300, Ezequiel Garcia wrote:
> On 15 Oct 09:17 AM, Antoine Tenart wrote:
> > /*
> > * Set the data and OOB size, depending on the selected
> > * spare and ECC configuration.
> > @@ -1538,6 +1660,19 @@ KEEP_CONFIG:
> > if (nand_scan_ident(mtd, 1, def))
> > return -ENODEV;
> >
> > + if (!pdata->keep_config) {
> > + ret = pxa3xx_nand_init(host);
> > + if (ret) {
> > + dev_err(&info->pdev->dev, "Failed to init nand: %d\n",
> > + ret);
> > + return ret;
> > + }
> > + }
> > +
> > + ret = pxa3xx_nand_config_flash(info);
> > + if (ret)
> > + return ret;
> > +
>
> Does this chunk belong to this patch? It wasn't here in the v2, and I believe
> it's not correct as you end up messing with the NDCR setting even if keep_config
> was passed.
You're right, it should be in "[3/4] mtd: pxa3xx_nand: rework flash
detection and timing setup". I made a mistake reworking the series...
And yes, pxa3xx_nand_config_flash() should be called before
"KEEP_CONFIG:".
Antoine
--
Antoine T?nart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 3/4] mtd: pxa3xx_nand: rework flash detection and timing setup
2015-10-15 7:17 [PATCH v3 0/4] mtd: pxa3xx_nand: rework the timing setup Antoine Tenart
2015-10-15 7:17 ` [PATCH v3 1/4] mtd: nand: allow compile test of MTD_NAND_PXA3xx Antoine Tenart
2015-10-15 7:17 ` [PATCH v3 2/4] mtd: pxa3xx_nand: add helpers to setup the timings Antoine Tenart
@ 2015-10-15 7:17 ` Antoine Tenart
2015-10-17 14:01 ` Ezequiel Garcia
2015-10-15 7:17 ` [PATCH v3 4/4] mtd: pxa3xx_nand: clean up the pxa3xx timings Antoine Tenart
2015-10-15 18:30 ` [PATCH v3 0/4] mtd: pxa3xx_nand: rework the timing setup Ezequiel Garcia
4 siblings, 1 reply; 15+ messages in thread
From: Antoine Tenart @ 2015-10-15 7:17 UTC (permalink / raw)
To: linux-arm-kernel
Rework the pxa3xx_nand driver to allow using functions exported by the
nand framework to detect the flash and the timings. Then setup the
timings using the helpers previously added.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
---
drivers/mtd/nand/pxa3xx_nand.c | 118 +++++++++--------------------------------
1 file changed, 25 insertions(+), 93 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index da52f21570cf..45e5e660d421 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -1363,45 +1363,16 @@ static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
return NAND_STATUS_READY;
}
-static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info,
- const struct pxa3xx_nand_flash *f)
+static int pxa3xx_nand_config_flash(struct pxa3xx_nand_info *info)
{
- struct platform_device *pdev = info->pdev;
- struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
struct pxa3xx_nand_host *host = info->host[info->cs];
- uint32_t ndcr = 0x0; /* enable all interrupts */
-
- if (f->page_size != 2048 && f->page_size != 512) {
- dev_err(&pdev->dev, "Current only support 2048 and 512 size\n");
- return -EINVAL;
- }
-
- if (f->flash_width != 16 && f->flash_width != 8) {
- dev_err(&pdev->dev, "Only support 8bit and 16 bit!\n");
- return -EINVAL;
- }
-
- /* calculate addressing information */
- host->col_addr_cycles = (f->page_size == 2048) ? 2 : 1;
-
- if (f->num_blocks * f->page_per_block > 65536)
- host->row_addr_cycles = 3;
- else
- host->row_addr_cycles = 2;
-
- ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
- ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
- ndcr |= (f->page_per_block == 64) ? NDCR_PG_PER_BLK : 0;
- ndcr |= (f->page_size == 2048) ? NDCR_PAGE_SZ : 0;
- ndcr |= (f->flash_width == 16) ? NDCR_DWIDTH_M : 0;
- ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
-
- ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
- ndcr |= NDCR_SPARE_EN; /* enable spare by default */
+ struct mtd_info *mtd = host->mtd;
+ struct nand_chip *chip = mtd->priv;
- info->reg_ndcr = ndcr;
+ info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
+ info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0;
+ info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0;
- pxa3xx_nand_set_timing(host, f->timing);
return 0;
}
@@ -1483,19 +1454,31 @@ static void pxa3xx_nand_free_buff(struct pxa3xx_nand_info *info)
}
#endif
-static int pxa3xx_nand_sensing(struct pxa3xx_nand_info *info)
+static int pxa3xx_nand_sensing(struct pxa3xx_nand_host *host)
{
+ struct pxa3xx_nand_info *info = host->info_data;
+ struct platform_device *pdev = info->pdev;
+ struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
struct mtd_info *mtd;
struct nand_chip *chip;
+ const struct nand_sdr_timings *timings;
int ret;
mtd = info->host[info->cs]->mtd;
chip = mtd->priv;
+ /* configure default flash values */
+ info->reg_ndcr = 0x0; /* enable all interrupts */
+ info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
+ info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
+ info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */
+
/* use the common timing to make a try */
- ret = pxa3xx_nand_config_flash(info, &builtin_flash_types[0]);
- if (ret)
- return ret;
+ timings = onfi_async_timing_mode_to_sdr_timings(0);
+ if (IS_ERR(timings))
+ return PTR_ERR(timings);
+
+ pxa3xx_nand_set_sdr_timing(host, timings);
chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
ret = chip->waitfunc(mtd, chip);
@@ -1580,12 +1563,8 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
struct pxa3xx_nand_info *info = host->info_data;
struct platform_device *pdev = info->pdev;
struct pxa3xx_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
- struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL;
- const struct pxa3xx_nand_flash *f = NULL;
struct nand_chip *chip = mtd->priv;
- uint32_t id = -1;
- uint64_t chipsize;
- int i, ret, num;
+ int ret;
uint16_t ecc_strength, ecc_step;
if (pdata->keep_config && !pxa3xx_nand_detect_config(info))
@@ -1594,7 +1573,7 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
/* Set a default chunk size */
info->chunk_size = 512;
- ret = pxa3xx_nand_sensing(info);
+ ret = pxa3xx_nand_sensing(host);
if (ret) {
dev_info(&info->pdev->dev, "There is no chip on cs %d!\n",
info->cs);
@@ -1602,53 +1581,6 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
return ret;
}
- chip->cmdfunc(mtd, NAND_CMD_READID, 0, 0);
- id = *((uint16_t *)(info->data_buff));
- if (id != 0)
- dev_info(&info->pdev->dev, "Detect a flash id %x\n", id);
- else {
- dev_warn(&info->pdev->dev,
- "Read out ID 0, potential timing set wrong!!\n");
-
- return -EINVAL;
- }
-
- num = ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1;
- for (i = 0; i < num; i++) {
- if (i < pdata->num_flash)
- f = pdata->flash + i;
- else
- f = &builtin_flash_types[i - pdata->num_flash + 1];
-
- /* find the chip in default list */
- if (f->chip_id == id)
- break;
- }
-
- if (i >= (ARRAY_SIZE(builtin_flash_types) + pdata->num_flash - 1)) {
- dev_err(&info->pdev->dev, "ERROR!! flash not defined!!!\n");
-
- return -EINVAL;
- }
-
- ret = pxa3xx_nand_config_flash(info, f);
- if (ret) {
- dev_err(&info->pdev->dev, "ERROR! Configure failed\n");
- return ret;
- }
-
- memset(pxa3xx_flash_ids, 0, sizeof(pxa3xx_flash_ids));
-
- pxa3xx_flash_ids[0].name = f->name;
- pxa3xx_flash_ids[0].dev_id = (f->chip_id >> 8) & 0xffff;
- pxa3xx_flash_ids[0].pagesize = f->page_size;
- chipsize = (uint64_t)f->num_blocks * f->page_per_block * f->page_size;
- pxa3xx_flash_ids[0].chipsize = chipsize >> 20;
- pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
- if (f->flash_width == 16)
- pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16;
- pxa3xx_flash_ids[1].name = NULL;
- def = pxa3xx_flash_ids;
KEEP_CONFIG:
if (info->reg_ndcr & NDCR_DWIDTH_M)
chip->options |= NAND_BUSWIDTH_16;
@@ -1657,7 +1589,7 @@ KEEP_CONFIG:
if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
nand_writel(info, NDECCCTRL, 0x0);
- if (nand_scan_ident(mtd, 1, def))
+ if (nand_scan_ident(mtd, 1, NULL))
return -ENODEV;
if (!pdata->keep_config) {
--
2.6.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 3/4] mtd: pxa3xx_nand: rework flash detection and timing setup
2015-10-15 7:17 ` [PATCH v3 3/4] mtd: pxa3xx_nand: rework flash detection and timing setup Antoine Tenart
@ 2015-10-17 14:01 ` Ezequiel Garcia
2015-10-19 9:32 ` Antoine Tenart
0 siblings, 1 reply; 15+ messages in thread
From: Ezequiel Garcia @ 2015-10-17 14:01 UTC (permalink / raw)
To: linux-arm-kernel
Antoine,
On 15 Oct 09:17 AM, Antoine Tenart wrote:
> Rework the pxa3xx_nand driver to allow using functions exported by the
> nand framework to detect the flash and the timings. Then setup the
> timings using the helpers previously added.
>
> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
> ---
> drivers/mtd/nand/pxa3xx_nand.c | 118 +++++++++--------------------------------
> 1 file changed, 25 insertions(+), 93 deletions(-)
>
This patch is not applying on l2-mtd.git master. Care to rebase it?
--
Ezequiel Garcia, VanguardiaSur
www.vanguardiasur.com.ar
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 3/4] mtd: pxa3xx_nand: rework flash detection and timing setup
2015-10-17 14:01 ` Ezequiel Garcia
@ 2015-10-19 9:32 ` Antoine Tenart
0 siblings, 0 replies; 15+ messages in thread
From: Antoine Tenart @ 2015-10-19 9:32 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Oct 17, 2015 at 11:01:44AM -0300, Ezequiel Garcia wrote:
> On 15 Oct 09:17 AM, Antoine Tenart wrote:
> > Rework the pxa3xx_nand driver to allow using functions exported by the
> > nand framework to detect the flash and the timings. Then setup the
> > timings using the helpers previously added.
> >
> > Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
> > ---
> > drivers/mtd/nand/pxa3xx_nand.c | 118 +++++++++--------------------------------
> > 1 file changed, 25 insertions(+), 93 deletions(-)
> >
>
> This patch is not applying on l2-mtd.git master. Care to rebase it?
I'll do this for the next version.
Antoine
--
Antoine T?nart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 4/4] mtd: pxa3xx_nand: clean up the pxa3xx timings
2015-10-15 7:17 [PATCH v3 0/4] mtd: pxa3xx_nand: rework the timing setup Antoine Tenart
` (2 preceding siblings ...)
2015-10-15 7:17 ` [PATCH v3 3/4] mtd: pxa3xx_nand: rework flash detection and timing setup Antoine Tenart
@ 2015-10-15 7:17 ` Antoine Tenart
2015-10-15 18:30 ` [PATCH v3 0/4] mtd: pxa3xx_nand: rework the timing setup Ezequiel Garcia
4 siblings, 0 replies; 15+ messages in thread
From: Antoine Tenart @ 2015-10-15 7:17 UTC (permalink / raw)
To: linux-arm-kernel
With the previous modifications, lots of pxa3xx specific definitions can
be removed.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
---
drivers/mtd/nand/pxa3xx_nand.c | 20 ++++++++------------
include/linux/platform_data/mtd-nand-pxa3xx.h | 11 +++--------
2 files changed, 11 insertions(+), 20 deletions(-)
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 45e5e660d421..ac197ca4ad5b 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -260,15 +260,14 @@ static struct pxa3xx_nand_timing timing[] = {
};
static struct pxa3xx_nand_flash builtin_flash_types[] = {
-{ "DEFAULT FLASH", 0, 0, 2048, 8, 8, 0, &timing[0] },
-{ "64MiB 16-bit", 0x46ec, 32, 512, 16, 16, 4096, &timing[1] },
-{ "256MiB 8-bit", 0xdaec, 64, 2048, 8, 8, 2048, &timing[1] },
-{ "4GiB 8-bit", 0xd7ec, 128, 4096, 8, 8, 8192, &timing[1] },
-{ "128MiB 8-bit", 0xa12c, 64, 2048, 8, 8, 1024, &timing[2] },
-{ "128MiB 16-bit", 0xb12c, 64, 2048, 16, 16, 1024, &timing[2] },
-{ "512MiB 8-bit", 0xdc2c, 64, 2048, 8, 8, 4096, &timing[2] },
-{ "512MiB 16-bit", 0xcc2c, 64, 2048, 16, 16, 4096, &timing[2] },
-{ "256MiB 16-bit", 0xba20, 64, 2048, 16, 16, 2048, &timing[3] },
+ { 0x46ec, 16, 16, &timing[1] },
+ { 0xdaec, 8, 8, &timing[1] },
+ { 0xd7ec, 8, 8, &timing[1] },
+ { 0xa12c, 8, 8, &timing[2] },
+ { 0xb12c, 16, 16, &timing[2] },
+ { 0xdc2c, 8, 8, &timing[2] },
+ { 0xcc2c, 16, 16, &timing[2] },
+ { 0xba20, 16, 16, &timing[3] },
};
static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
@@ -329,9 +328,6 @@ static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
.oobfree = { }
};
-/* Define a default flash type setting serve as flash detecting only */
-#define DEFAULT_FLASH_TYPE (&builtin_flash_types[0])
-
#define NDTR0_tCH(c) (min((c), 7) << 19)
#define NDTR0_tCS(c) (min((c), 7) << 16)
#define NDTR0_tWH(c) (min((c), 7) << 11)
diff --git a/include/linux/platform_data/mtd-nand-pxa3xx.h b/include/linux/platform_data/mtd-nand-pxa3xx.h
index ac4ea2e641c7..25538cfeee26 100644
--- a/include/linux/platform_data/mtd-nand-pxa3xx.h
+++ b/include/linux/platform_data/mtd-nand-pxa3xx.h
@@ -17,15 +17,10 @@ struct pxa3xx_nand_timing {
};
struct pxa3xx_nand_flash {
- char *name;
uint32_t chip_id;
- unsigned int page_per_block; /* Pages per block (PG_PER_BLK) */
- unsigned int page_size; /* Page size in bytes (PAGE_SZ) */
- unsigned int flash_width; /* Width of Flash memory (DWIDTH_M) */
- unsigned int dfc_width; /* Width of flash controller(DWIDTH_C) */
- unsigned int num_blocks; /* Number of physical blocks in Flash */
-
- struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
+ unsigned int flash_width; /* Width of Flash memory (DWIDTH_M) */
+ unsigned int dfc_width; /* Width of flash controller(DWIDTH_C) */
+ struct pxa3xx_nand_timing *timing; /* NAND Flash timing */
};
/*
--
2.6.1
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH v3 0/4] mtd: pxa3xx_nand: rework the timing setup
2015-10-15 7:17 [PATCH v3 0/4] mtd: pxa3xx_nand: rework the timing setup Antoine Tenart
` (3 preceding siblings ...)
2015-10-15 7:17 ` [PATCH v3 4/4] mtd: pxa3xx_nand: clean up the pxa3xx timings Antoine Tenart
@ 2015-10-15 18:30 ` Ezequiel Garcia
2015-10-16 6:38 ` Antoine Tenart
4 siblings, 1 reply; 15+ messages in thread
From: Ezequiel Garcia @ 2015-10-15 18:30 UTC (permalink / raw)
To: linux-arm-kernel
Ccing Robert as he can provide valuable test on PXA boards.
On 15 October 2015 at 04:17, Antoine Tenart
<antoine.tenart@free-electrons.com> wrote:
> Hi all,
>
> Let's try one more time to get this merged.
>
> Another series, introducing the Berlin nand support, depends on this.
>
> This series was part of a bigger one[1], which was split into smaller
> ones as asked by Ezequiel[2]. When we take this into account, this is
> v8.
>
> The aim here is to use the nand framework to setup the timings,
> while keeping the old in-driver way of configuration timings for
> compatibility reasons.
>
> You can find the series at:
> https://github.com/atenart/linux.git berlin/4.3/nand-timings
>
> Antoine
>
> Since v2:
> - Added back the support for keep-config 16 bits devices
> - Fixed wrong unit in a calculation
> - Reworked the pxa3xx_nand_init_timings() logic
> - Allowed compile test the pxa3xx driver
>
> Since v1:
> - Rebased on top of v4.2-rc1
>
> Since the series was split up:
> - Reworked the ndcr setup
> - Removed the read_id_bytes update after device detection
>
> Antoine Tenart (4):
> mtd: nand: allow compile test of MTD_NAND_PXA3xx
> mtd: pxa3xx_nand: add helpers to setup the timings
> mtd: pxa3xx_nand: rework flash detection and timing setup
> mtd: pxa3xx_nand: clean up the pxa3xx timings
>
> drivers/mtd/nand/Kconfig | 2 +-
> drivers/mtd/nand/pxa3xx_nand.c | 273 ++++++++++++++++----------
> include/linux/platform_data/mtd-nand-pxa3xx.h | 11 +-
> 3 files changed, 172 insertions(+), 114 deletions(-)
>
> --
> 2.6.1
>
>
> ______________________________________________________
> Linux MTD discussion mailing list
> http://lists.infradead.org/mailman/listinfo/linux-mtd/
--
Ezequiel Garc?a, VanguardiaSur
www.vanguardiasur.com.ar
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v3 0/4] mtd: pxa3xx_nand: rework the timing setup
2015-10-15 18:30 ` [PATCH v3 0/4] mtd: pxa3xx_nand: rework the timing setup Ezequiel Garcia
@ 2015-10-16 6:38 ` Antoine Tenart
2015-10-20 19:30 ` Robert Jarzmik
0 siblings, 1 reply; 15+ messages in thread
From: Antoine Tenart @ 2015-10-16 6:38 UTC (permalink / raw)
To: linux-arm-kernel
Hi Ezequiel,
On Thu, Oct 15, 2015 at 03:30:50PM -0300, Ezequiel Garcia wrote:
> Ccing Robert as he can provide valuable test on PXA boards.
Sorry for this, I tried to cc Robert but forgot when sending my
series...
Antoine
--
Antoine T?nart, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 0/4] mtd: pxa3xx_nand: rework the timing setup
2015-10-16 6:38 ` Antoine Tenart
@ 2015-10-20 19:30 ` Robert Jarzmik
0 siblings, 0 replies; 15+ messages in thread
From: Robert Jarzmik @ 2015-10-20 19:30 UTC (permalink / raw)
To: linux-arm-kernel
Antoine Tenart <antoine.tenart@free-electrons.com> writes:
> Hi Ezequiel,
>
> On Thu, Oct 15, 2015 at 03:30:50PM -0300, Ezequiel Garcia wrote:
>> Ccing Robert as he can provide valuable test on PXA boards.
>
> Sorry for this, I tried to cc Robert but forgot when sending my
> series...
Maybe for v4.
I appreciate even more git tree I can pull from, it eases my test procedure a
lot.
Cheers.
--
Robert
^ permalink raw reply [flat|nested] 15+ messages in thread