From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 38B0BC4332F for ; Wed, 23 Nov 2022 05:59:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:Subject:Message-ID:Date:From: In-Reply-To:References:MIME-Version:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=X7829nZJpGwZjulR9CcvPQAgQ8fsY/tU6m1iixAz9/8=; b=UaczZWIVOun4ka GZP6w+6M3pPXxCB4Kh2+XHMN+q/GX7kp6MgkUQnLFCpxG/p9ySdNgsUSkowxQfSPpd4eYVol1Kzog IsXvI+3T5eLAMw3nZloW+Wv/YPB2PnEFwdB3ktFTd1nwuGatQcd+Nr1tVetXrNNthAKfrlba1P1Gx OmCvfgDP0Jgt35azoKH8vLMLGj22wZ5hNiuffvQ9iCLKMMbwK6uQXrVkFMMaxxdnDr+lh/HjdM0Wu nwD6V/TcNbSWJ7sRj5xAWTaPMbhOm99yDKa0xbq4aK3uY1Cud9DbaN7pGCSeFHj0c9gmTHwLZLaoe 5MA0/FBy/kr8K5kKYrLQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1oximT-00EUyD-Tc; Wed, 23 Nov 2022 05:58:46 +0000 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1oximP-00EUrQ-W9 for linux-arm-kernel@lists.infradead.org; Wed, 23 Nov 2022 05:58:43 +0000 Received: by mail-pf1-x42e.google.com with SMTP id x66so7814247pfx.3 for ; Tue, 22 Nov 2022 21:58:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=1CLrxGHIryllbmQSGlgVdnSjWrEt46BNto6MWNDpJ/w=; b=QJP/DeqNLgu5BsGuGj3lQQO7TWZSEyZBCLjCsZ0Qh3Bh+h2X2TzepaUPMiA1uEhsS8 j8LnTgqxk9UWCub2wf3ch4lRUyNyI53tLZFh9wdYw1nfKn8RFFpGj2ZTq3pvVMskPV0L jAMsNd1lj1JzH0IAtTPJ/ZBwVQHf/7mFBP9mszx13lOa/KuWdi7ymtILHlPnZMwZ+wgN 8IAA6jRUNjSznBFXhDZJ8i/v95sgrfufd+2zSTk0O6kGOTvJPwp8Q0Lx/lrvQRaJifhR UE/jsEtrcKKRpLqXXeYkOVVdxZVtD2zu1B51d/Xon/dzDl9f1oXLoGNhdT35DAXeKAOJ 3plQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=1CLrxGHIryllbmQSGlgVdnSjWrEt46BNto6MWNDpJ/w=; b=nOxYzUkue/jYQHO0BkEyi5cL4TKP+OtWssnzxN5fhzMuSeB05cNcKMiKz8W3GWWEUW o6kR3ppWwrk2/PMAUzIlNyV618Uf/Bcc+9jreka4zLVywmF4fXbdTzREpzvHZXs6l7cn WjLAHMynh/gTZ30xGpc7F1y9jxmRsULsANvdBnTaGh7pGWnPVfdiEQaCKRta5XrCfvYQ 14n9U8UfN3OWG3JuZt0g1s4f8iWGqqn6lH+vutdy7gsPHSseQghZjX6x2PoQ0qYEi5za B6zIC8/jaqfHxqzpLYdyJqvfeItLWxgdIUAhTV3ttIZXRQNgSAEr9auuN8yBgHDde8ZP eFJQ== X-Gm-Message-State: ANoB5pnBu+O9Xq9wlugm4Z6NyNQK88lCjHzPdF0TgsLKRhikLaGyvDs+ uvjYEph0o3qbYV+iPeROTjsmu4OLV1iiNoGwJaUIuw== X-Google-Smtp-Source: AA0mqf5rcwSn/rDasVmz9NwN4rEesvQhcO7YEY2dJI9TMGCtzF5J3JarHfmU6aKvPVk6NYeUD56jm9Wf3vRxgbqxFw0= X-Received: by 2002:a05:6a00:27ab:b0:56c:71a4:efe with SMTP id bd43-20020a056a0027ab00b0056c71a40efemr11831681pfb.84.1669183114564; Tue, 22 Nov 2022 21:58:34 -0800 (PST) MIME-Version: 1.0 References: <20221113163832.3154370-1-maz@kernel.org> <20221113163832.3154370-14-maz@kernel.org> In-Reply-To: <20221113163832.3154370-14-maz@kernel.org> From: Reiji Watanabe Date: Tue, 22 Nov 2022 21:58:17 -0800 Message-ID: Subject: Re: [PATCH v4 13/16] KVM: arm64: PMU: Implement PMUv3p5 long counter support To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvmarm@lists.linux.dev, kvm@vger.kernel.org, James Morse , Suzuki K Poulose , Alexandru Elisei , Oliver Upton , Ricardo Koller X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20221122_215842_075186_AF179E3C X-CRM114-Status: GOOD ( 24.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, On Sun, Nov 13, 2022 at 8:46 AM Marc Zyngier wrote: > > PMUv3p5 (which is mandatory with ARMv8.5) comes with some extra > features: > > - All counters are 64bit > > - The overflow point is controlled by the PMCR_EL0.LP bit > > Add the required checks in the helpers that control counter > width and overflow, as well as the sysreg handling for the LP > bit. A new kvm_pmu_is_3p5() helper makes it easy to spot the > PMUv3p5 specific handling. > > Signed-off-by: Marc Zyngier > --- > arch/arm64/kvm/pmu-emul.c | 8 +++++--- > arch/arm64/kvm/sys_regs.c | 4 ++++ > include/kvm/arm_pmu.h | 7 +++++++ > 3 files changed, 16 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c > index 4320c389fa7f..c37cc67ff1d7 100644 > --- a/arch/arm64/kvm/pmu-emul.c > +++ b/arch/arm64/kvm/pmu-emul.c > @@ -52,13 +52,15 @@ static u32 kvm_pmu_event_mask(struct kvm *kvm) > */ > static bool kvm_pmu_idx_is_64bit(struct kvm_vcpu *vcpu, u64 select_idx) > { > - return (select_idx == ARMV8_PMU_CYCLE_IDX); > + return (select_idx == ARMV8_PMU_CYCLE_IDX || kvm_pmu_is_3p5(vcpu)); > } > > static bool kvm_pmu_idx_has_64bit_overflow(struct kvm_vcpu *vcpu, u64 select_idx) > { > - return (select_idx == ARMV8_PMU_CYCLE_IDX && > - __vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_LC); > + u64 val = __vcpu_sys_reg(vcpu, PMCR_EL0); > + > + return (select_idx < ARMV8_PMU_CYCLE_IDX && (val & ARMV8_PMU_PMCR_LP)) || > + (select_idx == ARMV8_PMU_CYCLE_IDX && (val & ARMV8_PMU_PMCR_LC)); Since the vCPU's PMCR_EL0 value is not always in sync with kvm->arch.dfr0_pmuver.imp, shouldn't kvm_pmu_idx_has_64bit_overflow() check kvm_pmu_is_3p5() ? (e.g. when the host supports PMUv3p5, PMCR.LP will be set by reset_pmcr() initially. Then, even if userspace sets ID_AA64DFR0_EL1.PMUVER to PMUVer_V3P1, PMCR.LP will stay the same (still set) unless PMCR is written. So, kvm_pmu_idx_has_64bit_overflow() might return true even though the guest's PMU version is lower than PMUVer_V3P5.) > } > > static bool kvm_pmu_counter_can_chain(struct kvm_vcpu *vcpu, u64 idx) > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index dc201a0557c0..615cb148e22a 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -654,6 +654,8 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r) > | (ARMV8_PMU_PMCR_MASK & 0xdecafbad)) & (~ARMV8_PMU_PMCR_E); > if (!kvm_supports_32bit_el0()) > val |= ARMV8_PMU_PMCR_LC; > + if (!kvm_pmu_is_3p5(vcpu)) > + val &= ~ARMV8_PMU_PMCR_LP; > __vcpu_sys_reg(vcpu, r->reg) = val; > } > > @@ -703,6 +705,8 @@ static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, > val |= p->regval & ARMV8_PMU_PMCR_MASK; > if (!kvm_supports_32bit_el0()) > val |= ARMV8_PMU_PMCR_LC; > + if (!kvm_pmu_is_3p5(vcpu)) > + val &= ~ARMV8_PMU_PMCR_LP; > __vcpu_sys_reg(vcpu, PMCR_EL0) = val; > kvm_pmu_handle_pmcr(vcpu, val); > kvm_vcpu_pmu_restore_guest(vcpu); For the read case of access_pmcr() (the code below), since PMCR.LP is RES0 when FEAT_PMUv3p5 is not implemented, shouldn't it clear PMCR.LP if kvm_pmu_is_3p5(vcpu) is false ? (Similar issue to kvm_pmu_idx_has_64bit_overflow()) } else { /* PMCR.P & PMCR.C are RAZ */ val = __vcpu_sys_reg(vcpu, PMCR_EL0) & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C); p->regval = val; } Thank you, Reiji > diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h > index 812f729c9108..628775334d5e 100644 > --- a/include/kvm/arm_pmu.h > +++ b/include/kvm/arm_pmu.h > @@ -89,6 +89,12 @@ void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu); > vcpu->arch.pmu.events = *kvm_get_pmu_events(); \ > } while (0) > > +/* > + * Evaluates as true when emulating PMUv3p5, and false otherwise. > + */ > +#define kvm_pmu_is_3p5(vcpu) \ > + (vcpu->kvm->arch.dfr0_pmuver.imp >= ID_AA64DFR0_EL1_PMUVer_V3P5) > + > u8 kvm_arm_pmu_get_pmuver_limit(void); > > #else > @@ -153,6 +159,7 @@ static inline u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1) > } > > #define kvm_vcpu_has_pmu(vcpu) ({ false; }) > +#define kvm_pmu_is_3p5(vcpu) ({ false; }) > static inline void kvm_pmu_update_vcpu_events(struct kvm_vcpu *vcpu) {} > static inline void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) {} > static inline void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) {} > -- > 2.34.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel