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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc; bh=V4bSpRziuje5o+7gdBCVWtLAAELBDhvrH2H1U3nqZI0=; b=8MINpAF/5YlwmFfDeyoGvnYg7QnBW9O3ugwxJv3S0DX6sDEn4Gmlql3dNqF263Eko7 LesAw46g6o481J+A6n8oWweJOExxWKeNmVliEPuPoCE1qWmsKEXf1GNIVblGj3Wlj4oE cZP6VNv9n1C6Dn8LcM+20QRbfuStubrYHdhIf1moV58sSkfIGETBYzANg5GzS3eyduHs CScDJ4yOiY4rM/rUHTe2P+SFFH+VbCKTKvJup8etwLOCMw8s6KsWHq6qxAW6wip5JJaX qdrHJ2jvMSz4Wd9qPtUPQmp5wkqW9w+OQdRR+rmYur3iPVy4LyGCOXLEfKWVnm58PFl0 Skzg== X-Gm-Message-State: ACgBeo17+WdP3gADHnwhU/U2BfElDlUSTiL1n14fYt3sZtpQXs6a66pk ngaWjmxz+rTuMlNXHrkBVUccbxSlkHyQa9GNg+tqWA== X-Google-Smtp-Source: AA6agR4BwjdlteSPdMbRx7NYLnCpMTRac4VWfKVgj3SObmnB5WEsoRlGSLWKRdvYNYXmXw42ZxTEbU4vIn1707ikLW8= X-Received: by 2002:ab0:154a:0:b0:39e:fee3:a65d with SMTP id p10-20020ab0154a000000b0039efee3a65dmr2738648uae.51.1661497300388; Fri, 26 Aug 2022 00:01:40 -0700 (PDT) MIME-Version: 1.0 References: <20220805135813.2102034-1-maz@kernel.org> <20220805135813.2102034-8-maz@kernel.org> In-Reply-To: <20220805135813.2102034-8-maz@kernel.org> From: Reiji Watanabe Date: Fri, 26 Aug 2022 00:01:24 -0700 Message-ID: Subject: Re: [PATCH 7/9] KVM: arm64: PMU: Allow ID_AA64DFR0_EL1.PMUver to be set from userspace To: Marc Zyngier Cc: Linux ARM , kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, kernel-team@android.com X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220826_000144_502933_7B5C9558 X-CRM114-Status: GOOD ( 28.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, On Fri, Aug 5, 2022 at 6:58 AM Marc Zyngier wrote: > > Allow userspace to write ID_AA64DFR0_EL1, on the condition that only > the PMUver field can be altered and be at most the one that was > initially computed for the guest. > > Signed-off-by: Marc Zyngier > --- > arch/arm64/kvm/sys_regs.c | 35 ++++++++++++++++++++++++++++++++++- > 1 file changed, 34 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index 55451f49017c..c0595f31dab8 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -1236,6 +1236,38 @@ static int set_id_aa64pfr0_el1(struct kvm_vcpu *vcpu, > return 0; > } > > +static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu, > + const struct sys_reg_desc *rd, > + u64 val) The function prototype doesn't appear to be right as the set_user of sys_reg_desc(). --- [From sys_regs.h] [sys_regs.h] int (*set_user)(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd, const struct kvm_one_reg *reg, void __user *uaddr); --- > +{ > + u8 pmuver, host_pmuver; > + > + host_pmuver = kvm_arm_pmu_get_host_pmuver(); > + > + /* > + * Allow AA64DFR0_EL1.PMUver to be set from userspace as long > + * as it doesn't promise more than what the HW gives us. We > + * don't allow an IMPDEF PMU though. > + */ > + pmuver = FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_PMUVER), val); > + if (pmuver == ID_AA64DFR0_PMUVER_IMP_DEF || pmuver > host_pmuver) > + return -EINVAL; As mentioned in my comments for the patch-6, the vCPU's PMUVER could currently be IMP_DEF. So, with this IMP_DEF checking, a guest with IMP_DEF PMU cannot be migrated to a newer KVM host. Do we need to tolerate writes of IMP_DEF for compatibility ? Oliver originally point this out for my ID register series, and my V6 or newer series tried to not return an error for this by ignoring the user requested IMP_DEF when PMU is not enabled for the vCPU (Instead, the field is set to 0x0). https://lore.kernel.org/all/20220419065544.3616948-16-reijiw@google.com/ Thank you, Reiji > + > + /* We already have a PMU, don't try to disable it... */ > + if (kvm_vcpu_has_pmu(vcpu) && pmuver == 0) > + return -EINVAL; > + > + /* We can only differ with PMUver, and anything else is an error */ > + val ^= read_id_reg(vcpu, rd, false); > + val &= ~(0xFUL << ID_AA64DFR0_PMUVER_SHIFT); > + if (val) > + return -EINVAL; > + > + vcpu->kvm->arch.dfr0_pmuver = pmuver; > + > + return 0; > +} > + > /* > * cpufeature ID register user accessors > * > @@ -1510,7 +1542,8 @@ static const struct sys_reg_desc sys_reg_descs[] = { > ID_UNALLOCATED(4,7), > > /* CRm=5 */ > - ID_SANITISED(ID_AA64DFR0_EL1), > + { SYS_DESC(SYS_ID_AA64DFR0_EL1), .access = access_id_reg, > + .get_user = get_id_reg, .set_user = set_id_aa64dfr0_el1, }, > ID_SANITISED(ID_AA64DFR1_EL1), > ID_UNALLOCATED(5,2), > ID_UNALLOCATED(5,3), > -- > 2.34.1 > > _______________________________________________ > kvmarm mailing list > kvmarm@lists.cs.columbia.edu > https://lists.cs.columbia.edu/mailman/listinfo/kvmarm _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel